AI Compute Cards Wiki Editorial

For the past three years, the entire AI hardware story was "training": who had the most H100s, who could connect a hundred thousand GPUs into a cluster. That race is essentially settled — NVIDIA won. But the next battlefield, "inference," is being fought under completely different rules: the measure is no longer peak FLOPS, but cost-per-token, latency, and power. In 2026, inference chips overtake training in scale for the first time, becoming the main battlefield of AI accelerators.

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1. Inference Becomes the Main Battlefield: 80%–90% of Compute Spent on Inference​

Training a large model costs hundreds of millions of dollars — once. But once the model goes live, it must answer billions of queries day after day. A popular consumer model may need tens of thousands of accelerators running 7×24 to keep up with demand. Therefore:

• Inference accounts for roughly 80%–90% of a model's lifecycle compute;
• Inference chips will make up about 60%–70% of the ~$400B AI accelerator market in 2026, up from only ~40% in 2023;
• Inference chip growth (estimated +52.7% YoY) significantly outpaces training chips (+28.4%); the share of inference-side compute demand exceeded training-side for the first time in 2026, reaching 54% (~$1010B).

The economics of inference are straightforward: training cost is amortized to near-zero, while inference cost becomes the entire bill. Every 1% cut in inference cost flows directly to profit — for a company whose inference traffic reaches hyperscale like OpenAI, the half of the bill is a number followed by a string of zeros.

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2. Market Size: Structural Growth Inflection Point Has Arrived​

Market	2026 Size	Growth	Notes
Global dedicated inference chips	$412.7B	+38.4%	14.2 pct higher growth than training chips
China dedicated inference chips	$118.6B (28.7% of global)	+44.1%	Strongest single market in APAC by growth
Global AI training/inference chips (incl. GPU/NPU)	exceeds $1850B	+40.2%	GPU ~62%

China's domestic substitution is accelerating, with domestic inference chips reaching 34.6% of shipments, up 9.8 pct from 2025.

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3. Technology-Axis Share Inverts: GPU Slows, ASIC Soars​

Axis	2026 Shipment Share	Trend
GPU	52.6%	Still leads, but growth slows to 22.7%
ASIC custom chips	41.3%	Up sharply from 17.8% in 2022
FPGA	Stable	Specific low-latency scenarios

Thanks to ecosystem maturity, GPU remains the mainstay, but NPU/ASIC already holds a 1.8× advantage over same-generation GPUs in energy efficiency, driving rapid adoption at the edge and on-device. Shipments of inference-optimized ASICs are expected to reach 11.5 million units, with unit cost about 35% lower than GPUs.

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4. Five Schools Clash​

School	Representative Products	Core Strength	Use Cases
General-purpose GPU	NVIDIA Rubin / B200 / H200	Mature ecosystem, train+infer unified	Frontier training + highly interactive inference
LPU (Language Processing Unit)	Groq LPU	Ultra-low latency, deterministic throughput	Real-time dialogue, high-concurrency inference
TPU (inference-specific)	Google TPU 8i (Zebrafish)	288GB HBM, 384MB on-chip SRAM, 19.2 Tb/s ICI	Google's scaled inference
Custom ASIC	OpenAI Jalapeno, Microsoft Maia 200, Meta MTIA	Strip generality tax for own models, ~50% lower cost/token	Hyperscaler's own workloads
Air-cooled inference card	Intel Crescent Island	350W air-cooled, 480GB LPDDR5X, tokens/watt	Cost-sensitive mid/long-tail inference

OpenAI's Jalapeno, co-developed with Broadcom, aims to cut inference token cost by roughly 50% versus a general-purpose GPU stack — the fifth member to join the "custom inference chip club" (after Google TPU, Amazon Inferentia/Trainium, Microsoft Maia, and Meta MTIA).

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5. Core Metric Shifts: cost-per-token and tokens/watt​

The fundamental difference between the inference race and the training race is the low switching cost:

• Training requires a 100k-GPU cluster + NVLink + CUDA, with extremely high migration cost;
• Inference is "embarrassingly parallel" at the endpoint level — no million-GPU cluster needed; a node that produces tokens fast and cheaply suffices, and is replaceable per endpoint.

This means NVIDIA's three moats (fastest silicon, NVLink scale-out, CUDA) are no longer absolute on the inference side. When the largest AI buyer (OpenAI) starts treating GPUs as "one of the options," the GPU premium begins to erode — pricing power relies on scarcity, and custom chips attack that scarcity from two directions at once: both reducing merchant-chip demand and giving buyers a credible external negotiation option.

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6. Edge and On-Device Explosion: Long-Tail Signal​

Demand shows significant long-tail and fragmentation:

Scenario	2026 Demand Size	Growth
Cloud inference	$198.2B (48%)	+24.5% (slowing)
Edge inference	$126.5B (30.7%)	+52.3%
On-device inference	$88.0B (21.3%)	+68.9%
Autonomous-driving inference	$67.3B	+58.2%
Industrial QA / robotics inference	$42.1B	+63.7%

The latency sensitivity and power constraints of inference workloads are reshaping chip architecture design priorities — which also explains why "air-cooled, large-memory" solutions like Crescent Island can find a niche.

Related Links​

• Hot Chips 2026 Full Recap
• Hyperscaler Custom Silicon Wave 2026
• NVIDIA Rubin Spec Page
• Intel Crescent Island Spec Page

References​

• Inference Chips vs Training Chips - ValueAdd VC
• Global and China Dedicated Inference Chip Industry In-Depth Research Report (2026) - IIM
• 2026 Global AI Training/Inference Chip Market and Trend Report - IIM
• Custom AI inference silicon: why OpenAI built Jalapeno - nexi.fund

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This article is compiled from publicly available 2026 market research, brokerage reports, and industry analysis. Market sizes and shares are third-party estimates with inconsistent methodologies and are for reference only.

The 2026 World Artificial Intelligence Conference (WAIC) was held July 17-20, 2026 at the Shanghai World Expo Center, themed "Intelligent Partners, Creating the Future Together." Over 1,100 companies showcased 3,000+ exhibits, with 300+ products debuting globally. For the compute-card industry, this concentrated review of domestic compute sent a clear signal: the competitive main line is shifting from "single-chip peak compute" to "SuperNode system-level effective compute."

1. Huawei Atlas 950 SuperPoD: live debut, wins SAIL grand award​

Huawei's Atlas 950 SuperPoD live hardware made its first public appearance at WAIC 2026, on-site carrying 16 compute cabinets with 1,024 Ascend cards total. With three system-level innovations — "ultra-wide bandwidth, ultra-low latency, unified memory addressing" — it stood out from hundreds of domestic and international entries to win the conference's top honor, the SAIL (Super AI Leader) Award.

Core parameters (confirmed on-site at WAIC)​

Metric	Atlas 950 SuperPoD
Exhibited scale	16 compute cabinets / 1,024 Ascend cards
Max interconnect scale	8,192 Ascend NPU cards fully interconnected (full config)
Interconnect protocol	Huawei in-house "Lingqu" (UnifiedBus) 2.0
Total compute	1 EFLOPS FP8 / 2 EFLOPS FP4 (1,024 cards); full 8,192-card ~8 EFLOPS FP8
Unified memory	256 TB globally unified memory address space
Interconnect latency	3 μs ultra-low RTT; TB-level NPU interconnect bandwidth
Full config	128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡, carrying 8,192 Ascend 950DT
Launch	Full config planned for Q4 2026
Cooling	Fully liquid-cooled blind-plug architecture

Huawei disclosed for the first time: the previous-gen Ascend 384 SuperNode has cumulatively shipped 750+ units commercially, deployed across 20+ industries including internet, operators, finance, education, healthcare, transportation, and manufacturing, calling it "the only domestic SuperNode that has trained SOTA models."

2. Software ecosystem: CANN fully open-sourced, developers at scale​

Beyond hardware, Huawei highlighted open-source software ecosystem progress:

• CANN heterogeneous compute architecture and MindSeries base software suite were fully open-sourced end of 2025;
• The CANN open-source community has incubated 67 projects, 12.44M+ lines of code, with 3,500+ monthly active developers;
• Huawei has co-developed 7,000+ solutions with 3,000+ industry partners, serving 2,000+ core government/enterprise customers;
• WAIC showcased 60+ real business scenarios, 20+ benchmark cases, covering the full chain from technology breakthrough to scaled commercial deployment.

3. Domestic chips' Day-0 adaptation becomes routine​

On July 6, 2026, Tencent released the MoE model Hunyuan T3 (295B parameters, 256K context); domestic chips rapidly completed Day-0 adaptation:

Vendor	Chip	Adaptation status
Moore Threads	MTT S5000	Completed rapid Hunyuan T3 adaptation (previously adapted DeepSeek-V4, GLM-5.2)
MetaX	Xiyun C series	In-house MXMACA stack first to full-chain Day-0 adaptation, zero-code deployment

Moore Threads also showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory."

4. More domestic compute debut highlights​

Vendor / product	Highlight
Orient AlphaChip DF1000	World's first "software-defined + near-memory computing" 3D chip, interconnect pitch compressed to sub-micron
ZhongHao XinYing "Xuyu"	Fully in-house next-gen TPU-architecture AI-specific chip, with Taize 2.0 server
Enflame × Iluvatar	Domestic high-performance Matrix SuperNode based on OEX+dOCS architecture, shortlisted for the conference "Excellent AI Leader Award"
Rongming Microelectronics	Advancing next-gen VPU, evolving from video processing to "visual-agent compute base"

The domestic AI chip lineup also included Moore Threads, MetaX, Enflame, Houmo, Cixiong, Suaneng, SemiDrive, Phytium, Aixin, Iluvatar, and others.

Industry interpretation: from "can it be built" to "is it used well"​

WAIC 2026 reflects a fundamental shift in the competitive stage of domestic AI chips:

1. SuperNode becomes the main battlefield: beyond single-chip performance, system-level capabilities — "inter-chip interconnect + cluster scale + cooling" — become the breakthrough key. Huawei Lingqu and Enflame/Iluvatar OEX are both pushing here. Huatai Securities defines 2026 as the "first year of domestic SuperNodes," estimating China's SuperNode architecture market could reach ¥341.4B by 2028, with 2026-2028 CAGR of 194%.
2. Software ecosystem delivers: Day-0 adaptation has gone from slogan to routine; the "launch-and-adapt" closed loop between domestic large models (DeepSeek-V4, GLM-5.2, Hunyuan T3) and domestic chips is essentially formed.
3. Demand-side endorsement: China Mobile earlier released its 2026-2027 AI SuperNode centralized procurement announcement — about 6,208 cards, over ¥2B — accelerating domestic SuperNode scaled commercialization.

Related links​

• Huawei Ascend 950DT specs
• Huawei Ascend 950PR specs
• Moore Threads MTT S5000 specs

References​

• Ascend 950 SuperNode live at WAIC 2026, wins SAIL top award - Global Times
• 2026 WAIC compute competition enters "system-level" battlefield, Ascend 950 SuperNode debuts - Tencent News
• Huawei unveils advanced Atlas 950 SuperPoD - China Daily
• Huawei Ascend 950 wins WAIC 2026 SAIL top honor - Huxiu
• Compute heavyweights at WAIC: Huawei Ascend 950 SuperNode live - 21st Century Business Herald

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This article is compiled from WAIC 2026 (July 17-20) on-site and official disclosures, and will continuously track the 950 SuperNode Q4 launch.

From December 2025 to July 2026 — just half a year — at least 6 AI chip companies have listed or are about to list on capital markets. Together with already-listed Cambricon, Hygon, and Iluvatar, the domestic GPU corps' total market cap is approaching ¥2 trillion. This marks the critical climb from domestic GPUs being "usable" to "useful."

1. The "Four Little Dragons" assemble on capital markets​

Company	Listing status	Raise / issue price	Sponsor
Moore Threads	Listed (STAR Market sh688795, 2025-12-05)	Issue price ¥114.28, raised ¥8B	CITIC Securities
MetaX	IPO accepted (2026-06-30)	¥3.904B (total investment ¥5B)	Huatai United
Enflame	Passed review (2026-06-15)	¥6B	—
Biren	HKEX / sprinting	—	—

Already-listed camp: Cambricon (sh688256, STAR Market 2020-07-20), Hygon, Iluvatar (HKEX). Moore Threads turned a book profit of ¥29.35M in Q1; MetaX narrowed losses 57.7% and gave a 2026 breakeven timeline.

2. Moore Threads MTT S5000: benchmarking against H100​

Moore Threads announced its flagship AI train+inference GPU MTT S5000 successfully completed full-pipeline adaptation validation of Zhipu's new-generation large model GLM-5 — measured performance "breaks the domestic compute ceiling":

Metric	MTT S5000
Architecture	4th-gen "Pinghu" architecture
FP8 compute	1 PFLOPS (1,000 TFLOPS)
Memory bandwidth	1.6 TB/s
Positioning	Full-function train+inference GPU, benchmarks against NVIDIA H100
Production	Mass-produced; clusters online supporting trillion-parameter training

Deployment validation: jointly completed full-pipeline training of embodied-brain model RoboBrain 2.5 with BAAI; partnered with SiliconFlow for high-performance DeepSeek-V3 inference, single-card speed near international top products. IPO funds go to three directions: next-gen AI train+inference chip, next-gen graphics chip, next-gen AI SoC chip.

WAIC 2026 new progress: Moore Threads showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory"; the company pre-announced H1 2026 revenue of ¥1.65B-1.75B, up 135%-149% YoY.

3. Cambricon: dual flagships MLU590/690​

Chip	Process	Compute	Memory	Customer / status
MLU590 (思元590)	7nm Chiplet	INT8 512 TOPS / FP16 345 TFLOPS	96 GB HBM2e	ByteDance inference mainstay, ~80% of A100 overall, mass shipments early 2026
MLU690 (思元690)	5nm-class (SMIC N+2)	FP16 700+ TFLOPS / INT8 2800+ TOPS	196 GB HBM3 (3.35 TB/s)	Dual-die packaging, MLU-Link 890 Gbps; ~70% of H100 (80-90% pure inference); ByteDance largest customer, mass production early 2026

Cambricon is the only domestic AI chip vendor with a "unified edge-cloud architecture" — one MLU instruction set spans 思元 220 (edge) → 370 (border) → 590/690 (cloud), with one NeuWare toolchain across compute tiers.

Capital and performance double explosion: Cambricon's total market cap exceeded ¥1 trillion on June 30, 2026, becoming the STAR Market's first "trillion-yuan stock," up 75%+ YTD. On performance, Q1 2026 revenue ¥2.885B (+160% YoY), deducted net profit ¥934M; full-year 2025 revenue ¥6.497B (+453% YoY), net profit attributable to parent ¥2.059B, ending long-term losses. ByteDance has cumulatively deployed over 100k 思元 590/690, its largest customer.

4. DeepSeek-V4 effect: changing the expectation coordinate system​

On April 24, 2026, DeepSeek released the trillion-parameter flagship DeepSeek-V4. Unlike a year earlier when V3's launch sparked debate over "can domestic chips even run large models," this time multiple domestic chips — Huawei Ascend, Cambricon, Hygon, MetaX, Moore Threads, Kunlun, T-Head, Iluvatar — completed adaptation on launch day.

The evaluation coordinate system is shifting: from "what percentage of NVIDIA's same-generation product performance" to "can it carry the real workloads of top-tier large models."

Industry interpretation​

1. Capital ammunition in place: dense IPOs provide ample funding for domestic GPU R&D iteration and capacity expansion, moving from "technology breakthrough" to "commercial virtuous cycle."
2. Train+inference becomes the mainstream route: Moore Threads takes the full-function GPU route (graphics+AI+general compute), differentiating from Huawei Ascend's "AI-focused."
3. Software ecosystem is the decider: Day-0 adaptation and the maturity of unified software stacks (MUSA / NeuWare / MXMACA) are replacing raw peak compute as the core yardstick of domestic GPU "usability."

Related links​

• Moore Threads MTT S5000 specs
• Cambricon MLU590 (思元590) specs
• Cambricon MLU690 (思元690) specs

References​

• Moore Threads flagship GPU benchmarked against NVIDIA H100 - Anue
• GPU Four Little Dragons take the stage, Cambricon no longer alone - Sina Finance
• GPU industry status and development trends (2026) - 10jqka
• 2026 domestic AI compute tracker (Huawei Ascend, Cambricon, Moore Threads)

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This article continuously tracks the domestic GPU listing process and product iteration.

The Ascend 950 series (950PR inference / 950DT training) has become the core supply of domestic AI compute. Per multiple brokerages and industry research, 950 series capacity is 100% booked with scarce spot supply; the full-year 1.2M-unit target is "100% certain," with expectations of an upward revision to 1.5M. This article summarizes capacity and order data as of July 2026.

1. Capacity pace: ~10× MoM jump in June​

Time	950PR monthly capacity	Notes
May 2026	50k-60k units	Near full production
June 2026	500k-600k units	~10× MoM; SMIC, Hua Hong tier-1 suppliers on overtime
Q3 2026 (est.)	700k-800k units	Per month
Full-year 2026 target	1.2M units	Upward revision to 1.5M expected

Supply chain delivery is tight: high-speed backplanes and liquid-cooling connectors' lead time stretched from 2 weeks to 6-8 weeks; orders are booked into 2027.

2. Order structure: top cloud providers + operators + overseas​

Customer	Locked volume	Amount / Notes
ByteDance	350k 950PR	$5.6B, concentrated delivery from Q3 2026
Tencent / Alibaba / Baidu	~250k 950PR + 150k 950DT	Combined ~400k units
Three major operators	200k+ units	Centralized procurement, for intelligent compute centers and AI private networks
Overseas	South Korea 2,000 units, Malaysia 3,000 servers, Russia ten-thousand-card cluster	From pilot to commercial

3. Shipment forecast: firmly #1 domestic​

Per CCA (Kezhi) Consulting estimates:

Metric	2025	2026 (forecast)
Huawei Ascend total shipments	812k cards	1.026M cards
Of which 950PR	—	~800k units
Of which 950DT	—	~100k-200k units

Huawei has completed the product transition from the 910 series to the 950 series. The internet industry has become Ascend's largest application market; competitive advantage is extending from single-hardware performance to software ecosystem and system capabilities.

4. Going overseas: formal South Korea entry in Q4​

Per Korean media ETNews, Huawei plans Q4 2026 to formally enter the South Korean market with the Ascend series and Atlas 950 SuperPod:

• Local distributor agreements signed; two channel partners including SK Shieldus selected
• Main products: 950PR (mass-produced and delivered since April) and 950DT (launched Q4)
• Official line: 950PR inference performance is 2.87× that of H20, priced at about 1/4 of it

5. WAIC 2026: 1024-card live debut confirmed​

At WAIC 2026 (July 17-20, Shanghai), Huawei's Atlas 950 SuperPoD live hardware made its first public appearance — a 16 compute-cabinet, 1,024 Ascend-card scale — and won the conference's top honor, the SAIL Award:

• Core metrics: total compute 1 EFLOPS FP8 / 2 EFLOPS FP4, 256 TB globally unified memory addressing, Lingqu 2.0 interconnect, 3 μs ultra-low RTT latency
• Full configuration: 128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡ footprint, carrying 8,192 Ascend 950DT, planned Q4 2026 launch
• Commercial foundation: previous-gen 384 SuperNode has cumulatively shipped 750+ units, deployed in 20+ industries
• Software ecosystem: CANN fully open-sourced end of 2025; community incubated 67 projects, 12.44M+ lines of code, 3,500+ monthly active developers

WAIC's debut confirmed the 950 series' "SuperNode-first" product logic: beyond single-card compute, system-level effective compute (interconnect bandwidth + unified memory + low latency) is the key dimension for domestic compute to benchmark against international flagships.

Ascend roadmap recap​

Product	Positioning	Key metrics (official roadmap)
950PR	Inference	1 PFLOPS (FP8) / 2 PFLOPS (FP4), 2 TB/s interconnect
950DT	Training	SuperNode core, launched Q4
960	Train/inference	2 PFLOPS (FP8) / 4 PFLOPS
970	Next-gen	In planning

Industry interpretation​

1. Domestic substitution moves from inference to training: 950PR (inference) ramps first, 950DT (training) follows in Q4, combined with the Atlas 950 SuperPoD ten-thousand-card interconnect — domestic compute now has the complete "training substitution" puzzle for the first time.
2. Capacity is the biggest variable: order certainty is extremely high, but SMIC/Hua Hong advanced-process capacity, HBM supply, and advanced packaging remain ramp bottlenecks — the root of "scarce spot supply."
3. Going overseas opens a second growth curve: bulk procurement from South Korea, Malaysia, Russia, and Latin America marks domestic compute's shift from "internal circulation" to "external circulation."

Related links​

• Huawei Ascend 950PR specs
• Huawei Ascend 950DT specs
• Huawei Ascend 950 specs

References​

• China intelligent-compute chip competitive landscape (CCA data) - IDCquan
• Ascend 950 series capacity and orders - Eastmoney
• WAIC catalyst: Huawei Ascend 950 SuperNode live debut - 10jqka
• Huawei Ascend 950 enters South Korea in Q4: 2.87× H20 inference - Toutiao

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Data in this article is based on official and major brokerage research; capacity/orders are dynamic figures and will be continuously updated.

July 2026, NVIDIA's next-gen AI compute platform Vera Rubin officially began its first shipments, succeeding the Blackwell architecture, with large-scale mass production planned for H2 2026. First customers include Microsoft, Google, Amazon, Meta, Oracle, and other large cloud providers.

1. World's First VR200 NVL72 Delivered (Milestone)​

CoreWeave jointly with Dell announced that the world's first NVIDIA Vera Rubin VR200 NVL72 cabinet has been officially delivered and passed the L11 full-cabinet hardware diagnostics on the first try. This marks Rubin's move from roadmap to physical product, with no major bottlenecks in core supply-chain links (HBM4, advanced packaging, liquid cooling, ultra-high-power power supply).

VR200 NVL72 Core Configuration​

Metric	Vera Rubin VR200 NVL72
Cabinet codename	Oberon
GPU	72 Rubin GPUs
CPU	36 Vera CPUs
Per-GPU memory	288 GB HBM4
Per-CPU memory	1.5 TB LPDDR5X
Total cabinet HBM4	20.7 TB (20,736 GB)
Total cabinet LPDDR5X	54 TB
Interconnect	NVLink 6 full mesh
Inference performance	~3.6 exaFLOPS class
Cooling	Liquid cooling
Generational improvement	~3.5× per-GPU compute, ~2.8× memory bandwidth (vs Blackwell)

Vera CPU integrates 88 custom Olympus ARM cores, with 1.8 TB/s interconnect to the GPU, usable as a GPU memory expansion pool. NVIDIA completed its first Vera CPU deliveries to Anthropic, OpenAI, xAI, and Oracle Cloud in May.

2. Samsung HBM4 Mass Production: Key Bottleneck Eases​

July 8, 2026, Samsung Electronics officially started HBM4 mass production for the Vera Rubin platform, with reported HBM4 mass-production yield reaching 70% (above the initial 60-65% expectation). Confirmation of this key supply-chain link clears obstacles for Rubin's large-scale deployment.

HBM Supply Landscape (2026 Q1)	Share
SK hynix	45%
Samsung	40%
Micron	15%

HBM4 uses 8-layer stacking (12-layer design planned for 2028), priced at about 2.8× HBM3e. TrendForce predicts HBM supply will grow 65% annually, with HBM4 reaching 35% of total output by 2027 Q4.

3. Rubin Ultra Sky-High Price: HBM Cost Dominates​

Per BofA Global Research estimates, the Rubin generation will push single-server cost to a new high:

Cost Item	Rubin VR200 (Oberon)	Comparison
Cabinet HBM4 usage	20,736 GB	—
HBM4 unit price	~$18.40 / GB	Blackwell (HBM3e) ~$11.26 / GB
HBM4 cost alone	~$382K	Excluding LPDDR5X
Rubin Ultra cabinet estimated price	~$21M	ITHome / BofA estimate

4. Rubin Ultra Design Change: Original 4-die Cancelled (per SemiAnalysis)​

Semiconductor research firm SemiAnalysis (2026-06-30) disclosed that the original 4-die Rubin Ultra GPU unveiled at GTC 2026 has been cancelled; the version actually shipping in 2027 is roughly halved in scale and performance:

• Reason for cancellation: The original integrated 4 compute dies + 16 HBM4E in a single CoWoS-L package; the substrate warped under the 4-die config, causing compute-die-to-substrate contact failure and yield collapse; the alternative CoPoS won't reach mass production until after late 2028, missing the 2027 node.
• New approach: Changed to dual-die (same construction as standard Rubin) + HBM4E, ~384 GB HBM4E per GPU (higher than standard Rubin's 288 GB), but total compute and bandwidth only half the original; to approach the original's aggregate compute, NVIDIA plans to assemble "2+2" board-level configs within the Kyber rack to reach four-die equivalent scale.
• Kyber rack delay: The companion Kyber NVL144 rack is delayed 12+ months to 2028 due to midplane PCB manufacturing difficulties; the 800V DC power scheme is likewise delayed to 2028.

⚠️ Note: NVIDIA has not commented officially on the above design change; some on X argue "the chip count hasn't changed, it's old news reheated." This section is compiled from SemiAnalysis public reports, subject to final NVIDIA disclosure. We have marked "specs pending official confirmation" on the Rubin Ultra preview card.

Industry Interpretation​

1. "Never doubt" moment realized: Rubin's first delivery passed L11 on the first try, dispelling market doubts about "Rubin delay," locking in H2 2026 AI compute supply certainty ahead of time.
2. Designed for Agentic AI: Rubin targets agentic workflows and ultra-long-context inference, further lowering the training/inference cost curve for trillion-parameter models.
3. HBM is the full-chain winner: 20.7 TB HBM4 per cabinet is enormous usage; SK hynix, Samsung, Micron, advanced packaging (CoWoS-L), liquid cooling, and power retrofitting all benefit across the chain, while also becoming the biggest cost and capacity constraint.

Related Links​

• NVIDIA Rubin R200 spec page
• NVIDIA Vera CPU spec page
• NVIDIA Rubin CPX spec page

References​

• Samsung Starts Mass Production for Nvidia's Vera Rubin AI Platform (2026-07-08)
• Rubin cabinet first delivery: CoreWeave and Dell deliver world's first VR200 NVL72
• Nvidia Rubin Ultra cabinet estimated at $21M - ITHome (2026-07-09)
• NVIDIA Vera Rubin scheduled for July 2026 shipment - VendorDeep

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This article continuously tracks Vera Rubin mass-production ramp and HBM4 supply-chain dynamics.

In the first half of 2026, the AI chip industry underwent a historic turning point — the center of gravity shifted from the "training race" to "inference efficiency," domestic chip market share broke 40% for the first time, NVIDIA built higher barriers with Blackwell Ultra, and the inference-specific chip track bloomed in diversity.

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I. Compute Doubles Again: NVIDIA Blackwell Ultra Launch (June 1)​

On June 1, 2026, NVIDIA CEO Jensen Huang unveiled the new-generation AI chip Blackwell Ultra at Computex 2026 (Taipei), setting a new starting line for the AI infrastructure race over the next two years.

Key Specs​

Metric	Blackwell Ultra	B200	Improvement
FP8 compute	20 petaFLOPS	~10 petaFLOPS	100%
Architecture	Blackwell Ultra	Blackwell	Upgrade
Expected delivery	2027 Q1	2026 Q1	—
Positioning	Hyperscale training + inference	Training + inference	Flagship

Industry Significance​

1. Direct impact of doubled compute: 20 petaFLOPS FP8 means training time for hundred-billion-parameter models drops sharply; trillion-parameter model training moves from "scientific experiment" to "engineering routine"
2. System-level balance: Blackwell Ultra is not just a chip but a system-level engineering breakthrough across NVLink, HBM, cooling, and power delivery
3. Roadmap certainty: The Q1 2027 delivery timeline lets cloud vendors and AI labs plan infrastructure budgets 18 months ahead

Challenges​

• Energy crisis: Doubled performance comes with sharply higher power; datacenter power and cooling design face extreme challenges
• Accessibility: Top-tier compute goes first to top cloud vendors; how smaller developers and research institutes reach compute at reasonable cost via cloud services
• Software stack adaptation: New hardware needs matching CUDA versions and framework support; software ecosystem maturity becomes the key bottleneck for compute conversion

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II. Domestic AI Chips: The Tipping Point from "Usable" to "Good"​

On June 16, 2026, Xinchuang World published "2026 China Domestic AI Chip Vendor Capability Quadrant", clearly outlining the overall domestic landscape.

2.1 Capability Quadrant Ranking​

Quadrant	Representative Vendors
Leader quadrant	Huawei Ascend, Hygon, Cambricon, Alibaba T-Head, Moore Threads
Visionary quadrant	Baidu Kunlunxin, Biren, Enflame, Iluvatar, HardyVision
Contender quadrant	TSINGMICRO, Black Sesame, SemiDrive, Lisuan, Houmo
Challenger quadrant	Denglin, Zhicun, VeriSilicon, Rockchip, Intellifusion

2.2 Huawei Ascend: The Anchor of Domestic Compute​

Market Position​

• In 2025, Ascend series shipped 812,000 units, capturing 49% of the domestic AI accelerator card share, firmly No.1 domestically
• Ascend 950PR single-card FP8 compute reaches 1P (PetaFLOPS), FP4 compute reaches 2P
• Inference performance is about 2.87x that of NVIDIA H20, priced at only 72,000-75,000 RMB, a significant price/performance advantage

Full-Stack Advantage​

Huawei's "device-network-cloud-chip" integrated strategy is Ascend's core moat:

• Chip design: Da Vinci 3.0 architecture iterating continuously
• OS: HarmonyOS/Euler OS deeply optimized
• Networking: Euler network protocol stack
• Cloud: Huawei Cloud ModelArts platform seamlessly integrated

Latest Progress​

• On June 5, 2026, Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, completed full-parameter post-training of a 1.6-trillion-parameter DeepSeek V4 Pro model on an Ascend 910C cluster
• This is the first time domestic AI chips completed trillion-parameter-level model training, marking "domestic substitution" moving from inference to training

2.3 Cambricon: The First Profitable Domestic AI Chip Benchmark​

Performance Explosion​

Metric	Full-year 2025	2026 Q1	YoY Growth
Revenue	6.497B RMB	2.885B RMB	+453% / +160%
Net profit	2.059B RMB (first annual profit)	1.013B RMB	— / +185%

Core Product: Siyuan 590​

• In DeepSeek R1 inference scenarios, TPS reaches 942, about 50% higher than H20
• Years of joint optimization with ByteDance; strongest short-term cloud inference deployment capability
• Of 2.885B RMB Q1 2026 revenue, Siyuan 590 contributed over 70%

Potential Risks​

Absent from the 2nd 2026 "Safe and Reliable Evaluation Results Announcement"; the reason is unclear and will affect its domestic government/enterprise market performance.

2.4 TSINGMICRO: The "Third Route" of Reconfigurable Chips​

Technical Route​

TSINGMICRO adopts a reconfigurable dataflow architecture同源 with Groq LPU, finding a balance between GPU generality and ASIC extreme efficiency.

Metric	TSINGMICRO TX81	Traditional GPU	Advantage
Inference cost	Baseline	+100%	Reduced 50%
Energy efficiency	Baseline	Baseline	3x improvement
Architecture	Reconfigurable dataflow	SIMT/SIMD	Better for inference

Deployment Progress​

• Cumulative shipments of reconfigurable chips exceed 30 million units
• Scaled deployment in a dozen-plus thousand-card-scale intelligent computing centers nationwide
• Has begun A-share IPO tutoring; likely to become the "first reconfigurable chip stock"

---

III. The Inference Chip Track: Core Signal of the Industry Shift​

On June 4, 2026, TrendForce published a deep report "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten," pointing out that the compute competition center of gravity is shifting from training to inference.

3.1 Why Now?​

Cost Structure Changed​

• Training is a one-time cost: Once a model is trained, marginal cost approaches zero
• Inference is a recurring cost: Every API call, every generated token represents compute consumption and gross-margin pressure
• Per-unit inference cost and energy efficiency directly affect gross margin and scale-expansion capability

Model Compression Tech Matured​

• 1.58-bit quantization and weight pruning let models maintain inference accuracy at extremely low memory footprint
• MoE (Mixture of Experts) architecture activates only a few expert sub-networks per inference via "partial wake-up," greatly reducing actual computation
• The rise of slimmed models provides commercial viability for hard-wired inference chips

3.2 NVIDIA's $20B Bet: Acquiring Groq (December 2025)​

On December 24, 2025, NVIDIA acquired Groq's inference technology license and core team for $20 billion, one of NVIDIA's largest M&A/tech acquisitions ever.

Strategic intent:

1. Fill the inference gap: NVIDIA GPU is unshakable in training, but inference efficiency was never its strongest suit
2. Counter specialized inference chips: Cerebras, Taalas, SambaNova and other startups are eroding the inference market
3. Position for Agentic AI: Agentic AI needs extremely low-latency, high-throughput inference

3.3 Taalas HC1: Proof of Concept for Hard-Wired Inference​

On February 20, 2026, Canadian AI chip startup Taalas launched inference chip Taalas HC1, directly etching Meta's open-source AI model Llama 3.1 8B into the chip.

Key Metrics​

Metric	Taalas HC1	NVIDIA B200 (throughput optimized)	Advantage
Inference rate	16,960 tokens/s/user	Baseline	~4-5x
Cost per million tokens	0.75 cents	3.79 cents	Reduced 80%
Power	~250W	~700W	Reduced 64%
Process	TSMC N6	TSMC 4nm	More mature
HBM	❌ Not used	✅ HBM3e	Lower cost

Technical Principle​

Taalas HC1 uses an aggressive Computing-in-Memory (CIM) implementation:

• Model weights directly固化 in Mask ROM (fully hardware-defined)
• On-chip SRAM handles dynamic data (KV cache and LoRA fine-tuning weights)
• Only 2 mask layers need modification to produce a dedicated chip for another AI model; turning an AI model into a physical chip takes only 2 months

Limitations​

• Lack of flexibility: Hard-wiring cannot cope with rapidly iterating model updates
• Ecosystem barrier: The current cloud market still relies on general-purpose platforms; customers may prefer flexible solutions that upgrade with models
• NRE cost: High one-time engineering cost, requiring sufficient deployment scale to amortize

3.4 Cerebras: The IPO Path of Wafer-Scale Integration​

On May 14, 2026, Cerebras Systems officially listed on NASDAQ, becoming the first wafer-scale AI chip company to go public.

Core Technology: Wafer-Scale Integration (WSI)​

• WSE-3 (third-gen wafer-scale engine): An entire 12-inch wafer as a single chip
• 44GB on-chip SRAM: No external HBM, eliminating the memory bandwidth bottleneck
• 21 PB/s bandwidth: On-chip communication bandwidth, thousands of times that of GPUs
• Partnership with OpenAI: Signed a 3-year, 750MW, $20B+ compute cooperation agreement

IPO Significance​

Cerebras's listing marks the maturation of the inference-specific chip track:

1. Capital markets begin pricing such companies
2. Proves "non-GPU" technical routes have commercial viability
3. Provides valuation references for other inference chip startups (Groq, SambaNova, Taalas, etc.)

3.5 Inference Chip Landscape: Multiple Technical Routes Coexist​

Company	Technical Route	Core Advantage	Representative Product
Taalas	Hard-wired (Mask ROM)	Extreme inference efficiency, low cost	HC1
Cerebras	Wafer-scale integration (WSI)	Ultra-high bandwidth, large-model inference	WSE-3
Groq	SRAM-first architecture	Deterministic latency, high throughput	LPU (acquired by NVIDIA)
d-Matrix	Digital in-memory compute (DIMC)	More flexible than hard-wiring	Corsair
Etched	Hard-wired Transformer	Works for all Transformer models	Sohu
Axelera AI	Digital in-memory compute (D-IMC) + RISC-V	High energy efficiency	Metis AIPU

TrendForce predicts:

• General-purpose GPUs still dominate training and multi-model environments
• But in mature, predictable scenarios, general-purpose GPU profit margins will be compressed
• The industry shifts from general compute monopoly to a dual-track structure of general + specialized coexistence

---

IV. Overall Domestic AI Chip Landscape in H1 2026​

4.1 Industry Enters Scale-Up Phase​

Metric	2025	2026 Q1	Trend
Domestic AI accelerator shipments	1.65M units (41% share)	—	Rising
Total China AI accelerator shipments	~4M units	—	—
Hygon revenue growth	—	Doubled	↑
Cambricon revenue growth	—	+160%	↑
Moore Threads revenue growth	—	Doubled	↑

Leading vendors collectively entered the revenue realization channel, moving from "technical validation" to "scale commercialization."

4.2 Three Core Development Trends​

Trend 1: Capitalization Wave Reshapes the Landscape​

• Late 2025 to early 2026: Moore Threads, Iluvatar listed on the STAR Market
• Biren listed on the Hong Kong stock exchange
• Enflame STAR Market IPO accepted
• Kunlunxin, T-Head initiated listing processes
• TSINGMICRO, HardyVision and others advancing IPOs

Capitalization brings dual effects:

• ✅ Positive: Supports R&D and ecosystem building
• ⚠️ Negative: Valuation bubbles and revenue realization pressure

Trend 2: Capacity Becomes the Biggest Constraint Variable​

The contradiction between explosive domestic AI chip demand and limited advanced-process capacity is sharpening:

Vendor	Advanced-process capacity need	Actually obtained
Huawei Ascend	15K wafers/month (7nm-class)	Priority guaranteed
SMIC total capacity	~20K wafers/month (7nm-class)	—
Other vendors	~5K wafers/month combined	Extremely tight

Whether stable wafer capacity can be secured directly determines vendor survival. Cambricon's 75.4% inventory-to-revenue ratio is essentially a lock on capacity.

Trend 3: Competition Shifts from "Usable" to "Good"​

Early competition focused on "can it run the model"; now it's about "runtime efficiency, deployment cost":

Dimension	"Usable" era	"Good" era
Hardware performance	Can it run the model	Runtime efficiency, energy efficiency
Software stack	Basic adaptation	Maturity, framework breadth
Ecosystem	Existence	Developer community activity
Deployment cost	Insensitive	Core competitive factor

---

V. H2 2026 Outlook​

5.1 Upcoming Key Events​

Time	Event	Impact
2026 Q3	NVIDIA Rubin architecture details revealed	Next-gen flagship specs unveiled
2026 Q3	Huawei Ascend 950PR/950DT formally launched	New benchmark for domestic inference chips
2026 Q4	AMD MI350X scaled delivery	NVIDIA Blackwell competitor
2026 Q4	Cambricon Siyuan 690 launch (est.)	New-gen training chip
2027 Q1	NVIDIA Blackwell Ultra delivery	New compute benchmark lands

5.2 Key Competitive Factors Over the Next Three Years​

1. Wafer capacity access: Advanced-process capacity is a scarce resource; vendors tied to SMIC and TSMC have inherent advantages
2. Capital operation efficiency: The IPO window is limited; raising enough capital on the market determines R&D sustainability
3. Software ecosystem depth: Hardware performance is only the entry ticket; software stack maturity, framework adaptation breadth, and developer community activity are the core moat

---

VI. Conclusion: A Diverse Ecosystem Will Eventually Form​

In H1 2026, the AI chip industry is undergoing a historic transition from "one dominant player" to "pluralistic coexistence."

• NVIDIA builds higher training barriers with Blackwell Ultra while laying out inference efficiency via the Groq acquisition
• Huawei Ascend holds the domestic compute baseline with full-stack capability; 950PR begins to surpass H20 in inference
• Cambricon proves the commercial viability of domestic AI chips by turning profitable first; Siyuan 590 surpasses international rivals in specific scenarios
• Cerebras, Taalas and other inference-specific chip companies opened a "non-GPU" third route
• TSINGMICRO's reconfigurable architecture provides a diversified technical route choice for China's AI chips

Over the next three years, the domestic AI chip endgame will form a pluralistic ecosystem where GPU, ASIC, and reconfigurable computing three technical routes coexist, with cloud and edge developing in coordination. "Domestic substitution" is no longer a slogan, but an industrial reality happening now.

---

Data sources:

• Xinchuang World "2026 China Domestic AI Chip Vendor Capability Quadrant" (2026-06-16)
• TrendForce "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten" (2026-06-04)
• RayByte "Compute Doubles! NVIDIA Blackwell Ultra Chip Launched" (2026-06-02)
• Official financial reports and announcements of each company

Related reading:

• Huawei Ascend 910C Specs Deep Dive
• Full Comparison Table

---

June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

---

2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

---

3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

---

4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

---

5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

---

Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

---

Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

---

References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

---

This article is continuously updated. Please provide the latest developments.

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights​

• MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
• MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
• Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
• Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
• Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
• Architecture upgrade: from CDNA 4 to CDNA 5
• Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs​

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

Model	Positioning	Memory	FP4 compute	FP8 compute	TDP (est.)
MI455X	Flagship training+inference	432GB HBM4	40 PFLOPS	20 PFLOPS	~1,000W
MI450	Cost-performance training	288GB HBM4	28 PFLOPS	14 PFLOPS	~800W
MI440X	Enterprise inference	216GB HBM4	25 PFLOPS	12.5 PFLOPS	~600W
MI430X	HPC / scientific computing	192GB HBM4	20 PFLOPS	10 PFLOPS	~500W
MI400X	General / edge inference	128GB HBM4	12 PFLOPS	6 PFLOPS	~400W

Key upgrades (vs MI350 series):

• Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
• Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
• Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +2×)
• Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
• Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X​

Metric	MI355X (2025)	MI455X (2026)	Improvement
FP4 compute	20 PFLOPS	40 PFLOPS	2×
FP8 compute	10 PFLOPS	20 PFLOPS	2×
Memory capacity	288GB HBM3e	432GB HBM4	1.5×
Memory bandwidth	8 TB/s	19.6 TB/s	2.45×
Process	TSMC 3nm	2nm + 3nm hybrid	New gen
Architecture	CDNA 4	CDNA 5	New gen
TDP	800-1000W	~1,000W	Flat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail​

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades​

1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
4. Native sparsity support: MoE Expert-Parallel optimization
5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin​

Metric	AMD MI455X	NVIDIA B200	NVIDIA Rubin R200 (2026 Q4)
FP4 compute	40 PFLOPS	20 PFLOPS (45 sparse)	~40 PFLOPS (est.)
FP8 compute	20 PFLOPS	10 PFLOPS (22.5 sparse)	~20 PFLOPS (est.)
Memory	432GB HBM4	192GB HBM3e	288GB HBM4
Memory bandwidth	19.6 TB/s	8 TB/s	13 TB/s
TDP	~1,000W	700-1000W	~1,000W
Process	2nm + 3nm hybrid	TSMC 4np	TSMC 3nm
Mass production	2026 Q4	2024 Q4	2026 Q4
Software ecosystem	ROCm	CUDA	CUDA
Strength	Memory capacity, open ecosystem	Most mature ecosystem	Next-gen architecture
Weakness	Software ecosystem gap	Smaller memory	Not yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline​

Time	Event
June 12, 2025	MI400 series specs first announced at Advancing AI
January 5, 2026	MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3	MI450 sampling begins
2026 Q4	MI455X mass production
2026 Q4	MI440X (enterprise inference) launched
2027 Q1	MI430X/MI400X (HPC/edge inference) launched
2027	MI500 series (next gen)

AMD AI chip roadmap (2025-2027)​

Time	Product	Process	Notes
Q4 2024	MI325X	TSMC 5nm	HBM3e upgraded
Q3 2025	MI355X (MI350 series)	TSMC 3nm	CDNA 4, 288GB HBM3e
Q4 2026	MI455X (MI400 series)	2nm + 3nm hybrid	CDNA 5, 432GB HBM4
Q1 2027	MI500 series	TSMC 2nm (est.)	Next gen, further gains

Software ecosystem: ROCm's progress and challenges​

✅ Progress​

• PyTorch 2.5+: native MI300X/MI455X support
• Hugging Face Transformers: official AMD GPU support
• vLLM 0.8+: MI300X inference support (experimental)
• JAX: AMD adapting (vs Google TPU)

⚠️ Challenges​

• Framework optimization: PyTorch on AMD GPUs still below NVIDIA
• Operator coverage: some niche operators need hand-written HIP
• Multi-card communication: RCCL (vs NCCL) still lags
• Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison​

Vendor	Product	FP4 compute	Memory	Mass production	Strength	Weakness
AMD	MI455X	40 PFLOPS	432GB HBM4	2026 Q4	Largest memory, open ecosystem	Software gap
NVIDIA	B200	20 PFLOPS	192GB HBM3e	2024 Q4	Most mature ecosystem	Smaller memory
NVIDIA	Rubin R200	~40 PFLOPS	288GB HBM4	2026 Q4	Next-gen architecture, CUDA	Expensive
Huawei	Ascend 910C	~1.6 PFLOPS	64GB HBM	2026 Q2	China-localized	Export-controlled
Google	TPU 8t	~9.2 PFLOPS	~256GB HBM3e	Late 2027	Gemini-integrated	Google Cloud only

Industry impact​

1. Impact on NVIDIA​

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

• NVIDIA has the CUDA ecosystem moat
• NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
• AMD only sells cards/nodes, NVIDIA sells AI factories
• MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips​

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

• Catch up to 5nm + HBM3e by 2026-2027
• Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers​

MI455X gives cloud providers a second option beyond NVIDIA:

• Microsoft Azure: already deployed MI355X, may follow with MI455X
• Google Cloud: in-house TPU, won't use AMD
• Amazon AWS: in-house Trainium/Inferentia, won't use AMD
• Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

Related chips​

• AMD MI455X - the new launch
• AMD MI300X - previous flagship
• AMD MI325X - HBM3e upgraded
• NVIDIA B200 - direct competitor
• NVIDIA Rubin R200 - same-generation competitor

References​

• MI455X chip - Baidu Baike - official specs
• AMD drops its most powerful two-gen AI chips! World's first 432GB HBM4 - Zhihu - on-site report
• Taking on NVIDIA: AMD launches MI440X for enterprise AI data centers - Tencent News
• AMD MI400 packs 432GB HBM4: specs crush NVIDIA on paper - CocoLoop
• AMD CES 2026 keynote replay

---

This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).

On April 22, 2026, at Google Cloud Next '26 in Las Vegas, Google officially launched its 8th-generation Tensor Processing Unit (TPU). For the first time in Google's history, it split AI training and inference onto two independent chips:

• TPU 8t: designed for model training
• TPU 8i: focused on high-concurrency inference

This launch introduces no new physical concept, but focuses on solving the core pain points of AI data centers: ten-thousand-card cluster scaling efficiency, Agentic AI workload optimization, and performance per watt.

TPU 8i (inference-specific): eliminating the "waiting room effect"​

TPU 8i is the first inference-specific chip co-designed by Google and MediaTek, aimed at eliminating the "waiting room effect" — where user requests are intentionally queued or delayed to maximize hardware utilization.

TPU 8i core specs (estimated)​

Parameter	TPU 8i	TPU v7 Ironwood
Positioning	Inference-specific	Mostly inference
Process	TSMC 2nm	—
Die design	Dual compute die (est.)	—
Memory	8× HBM3e 12-layer (~192GB est.)	8× HBM3 (192GB)
Memory bandwidth	~7 TB/s (est.)	7,380 GB/s
FP8 compute	~4,614 TFLOPS (est.)	4,614 TFLOPS
TDP (per chip)	1,300 W	1,000 W
Interconnect	ICI 3D Torus	ICI 3D Torus
Integrated CPU	Arm Axion (64 cores)	None
Cooling	Air or liquid	4th-gen liquid
Announced	2026-04-22	2025-08-25
Mass production	End of 2027	2026

Key features:

• ✅ High-concurrency inference optimization: built for Agentic AI, supports inference chains of thousands of steps
• ✅ Arm Axion CPU integration: 64-core Neoverse V2, host CPU + data preprocessing synergy
• ✅ Low latency: eliminates the "waiting room effect", extremely low TTFT (time to first token)
• ✅ 117% better performance per watt: vs Ironwood (at equal price)

TPU 8t (training-specific): the "engine" of Gemini 3/4​

TPU 8t is designed for training Google's frontier models like Gemini 3 / Gemini 4, continuing Google's long-term partnership with Broadcom.

TPU 8t core specs​

Parameter	TPU 8t	TPU v7 Ironwood	Improvement
Positioning	Training-specific	Mostly inference	Form-factor split
Process	TSMC 2nm	—	New gen
Die design	Dual compute die	—	Architecture upgrade
Memory	8× HBM3e 12-layer (~256GB per chip est.)	8× HBM3 (192GB)	Upgrade
Memory bandwidth	~7 TB/s (per chip est.)	7,380 GB/s	Flat
Pod chip count	9,600 chips	9,216	+4%
Pod total HBM	2 PB	—	Far exceeds
Pod FP4 compute	121 EFLOPS	~42 EFLOPS (est.)	~3×
Integrated CPU	Arm Axion (64 cores)	None	New
TDP (per chip)	1,300 W	1,000 W	+30%
Mass production	End of 2027	2026	—

Key features:

• ✅ Native MoE training support: Expert-Parallel optimization (DeepSeek / Mixtral style)
• ✅ Long-context training: 1M+ token context training optimization
• ✅ RLHF / post-training: native Online RL (DPO/PPO/GRPO) optimization
• ✅ Arm Axion CPU synergy: data preprocessing / weight init offloaded to CPU
• ✅ SparseCore acceleration: MoE routing and recommendation systems

Strategic significance of the 8th-generation TPU​

1. Training and inference split for the first time​

Previously, Google's TPU design philosophy was "one architecture for both training and inference" (e.g., TPU v5p, v6e). But the arrival of the Agentic AI era changed that:

• Training workloads: large-scale matrix multiply, long-sequence backpropagation, sparse MoE
• Inference workloads: high concurrency, low latency, KV Cache-intensive, dynamic batching

These two workloads impose very different demands on chip architecture. After the split:

• TPU 8t can focus on optimizing compute density and memory capacity
• TPU 8i can focus on optimizing inference throughput and performance per watt

2. Dual-track partnership with Broadcom and MediaTek​

• Broadcom: continues designing TPU 8t (training), extending the long-term partnership since TPU v1
• MediaTek: first-time collaboration designing TPU 8i (inference), bringing mobile-chip low-power design expertise

This "dual-track" strategy lets Google:

• Pursue peak performance on training chips (combined with Broadcom's high-end ASIC experience)
• Pursue peak energy efficiency on inference chips (combined with MediaTek's mobile-chip experience)

3. Versus NVIDIA Vera Rubin​

Comparison	Google TPU 8t + 8i	NVIDIA Vera Rubin
Strategy	Training/inference split	Unified architecture (GPU+CPU)
Process	TSMC 2nm	TSMC 3nm (est.)
Ecosystem	Google Cloud only	Globally available
Software	JAX / PyTorch-XLA	CUDA / PyTorch
Mass production	End of 2027	Fall 2026
Strength	Deep Gemini integration	Most mature ecosystem

Deep technical analysis​

TSMC 2nm: why 2nm?​

Google is the first vendor to adopt TSMC 2nm on an AI accelerator (NVIDIA Rubin uses 3nm). 2nm (N2) vs 3nm (N3E):

• Transistor density: ~15-20% higher
• Power reduction: ~25-30% (at equal performance)
• Performance gain: ~10-15% (at equal power)

For TPU 8t/8i, which already hit 1,300W, 2nm is mandatory — otherwise 4nm/3nm couldn't integrate dual compute dies and 8× HBM3e within reasonable power.

Arm Axion CPU: Google's in-house CPU enters the TPU node for the first time​

Previously, TPU nodes used Intel Xeon or AMD EPYC as host CPUs. TPU 8t/8i integrate Google's in-house Arm Axion CPU (64-core Neoverse V2) for the first time:

Significance:

1. Data preprocessing offload: tokenization, data augmentation can run entirely on Axion, freeing TPU compute
2. Weight initialization: large-model training weight init on CPU, accelerating training startup
3. Inference scheduling: Axion handles request scheduling and load balancing for multi-model inference

This marks the TPU node's evolution toward a "SuperNode": no longer a pure accelerator, but a TPU + Axion CPU co-design system, comparable to NVIDIA's Vera CPU.

4th-gen liquid cooling: the 1,300W thermal challenge​

TPU 8t/8i TDP reaches 1,300W (30% over Ironwood's 1,000W), posing a huge data-center cooling challenge.

Google adopts a 4th-gen liquid cooling solution:

• Cold-plate liquid cooling: directly cools GPU die and HBM
• Immersion cooling: optional (ultra-high-density deployment)
• Smart thermal control: dynamically adjusts pump speed and fan RPM by workload

Production timeline and use cases​

Time	Event
2026-04-22	Cloud Next '26 official announcement
H2 2026	Internal testing (Google DeepMind first)
End of 2027	Mass production, Google Cloud availability
2028	Next-gen TPU (possibly TPU 9)

Target use cases:

• ✅ Frontier model training (Gemini 3/4, external customers)
• ✅ MoE large-model inference (high concurrency, low latency)
• ✅ Multimodal AI (ViT + LLM simultaneous inference)
• ✅ Agentic AI (Agentic AI workloads)

Competitive comparison​

Vendor	Product	Process	TDP	Mass production
Google	TPU 8i (inference)	TSMC 2nm	1,300W	End of 2027
Google	TPU 8t (training)	TSMC 2nm	1,300W	End of 2027
NVIDIA	Rubin GPU	TSMC 3nm (est.)	~1,000W	Fall 2026
NVIDIA	Vera CPU	TSMC 3nm (est.)	~500W	Fall 2026
AMD	MI455X (MI400)	TSMC 3nm (est.)	~700W	2026
Huawei	Ascend 950PR	—	~500W	Q1 2026

Industry impact​

1. AI chips enter the 2nm era: Google leads with TSMC 2nm; NVIDIA and AMD will follow
2. Training/inference split becomes a new trend: other vendors (NVIDIA, AMD) may follow suit
3. In-house CPUs become standard: Google (Axion), NVIDIA (Vera), Huawei (Kunpeng) all do CPU+accelerator co-design
4. Liquid cooling becomes inevitable: 1,300W TDP means air cooling can no longer suffice

Related chips​

• Google TPU 8i - inference-specific TPU detailed specs
• Google TPU 8t - training-specific TPU detailed specs
• Google TPU v7 Ironwood - previous-gen inference TPU
• NVIDIA Rubin R200 - same-generation competitor
• NVIDIA Vera CPU - counterpart to Google Axion

References​

• Google blog: Introducing new TPUs at Cloud Next '26
• Google Cloud Next '26 keynote replay
• Tencent News: Google 8th-gen TPU deep dive

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This article is compiled from Google's official announcements and public sources; some specs are estimates, subject to final official release.

On June 5, 2026, Shenzhen announced a major piece of news: Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, used 1,000 Huawei Ascend 910C chips to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model.

This was no tentative attempt, but a milestone technological breakthrough. It proved with irrefutable engineering results that: domestic AI chips are fully capable of supporting world-class, super-large-parameter model training.

Why this matters​

The two thresholds of AI chips: "inference" and "training"​

• Inference: using an existing model to chat, write copy. Domestic chips could already do this
• Training: adjusting model parameters to learn new capabilities. Full-parameter training adjusts all 1.6 trillion parameters at once — maximum difficulty

Previously, full-parameter training of trillion-scale models was monopolized by NVIDIA H100/H200. Domestic chips could only do inference, not large-scale training.

The significance of this breakthrough: domestic compute leapt from "usable" to "useful", from "inference" to "training".

Technical details​

Training configuration​

Item	Parameter
Chips	Huawei Ascend 910C × 1,000
Model	DeepSeek-V4-Pro
Parameters	1.6 trillion (1600B)
Training type	Full-parameter post-training
Framework	MindSpore + torch_npu
Completed	Announced June 5, 2026

Performance metrics​

Metric	Value	Assessment
Compute utilization	>30%	Industrial grade (top overseas chips ~40%)
Key training operator efficiency	+14%	vs previous-gen 910B
Communication bandwidth utilization	>60% (est.)	MoE All-to-All communication
Stability	1,000 cards trained continuously with no failures	Cluster stability met standard

💡 About 30% compute utilization: many feel 30% is low, but in large-model training this is already a very respectable industrial-grade level. Even with the most advanced overseas chips, many teams' actual utilization is around 40%.

Ascend 910C detailed specs​

Ascend 910C is Huawei's AI training/inference chip announced at the Huawei Analyst Conference (April 24, 2024), with a theoretical peak of 800 TFLOPS (BF16), in the same class as NVIDIA H100.

Parameter	Ascend 910C	Ascend 910B	NVIDIA H100
Architecture	Ascend 910C	Ascend 910B	Hopper
Process	TSMC 7nm (est.)	TSMC 7nm	TSMC 4NP
BF16 compute	800 TFLOPS	256 TFLOPS	989 TFLOPS (sparse)
Memory	64GB HBM (est.)	64GB HBM2e (B1/B2)	80GB HBM3
Memory bandwidth	~2TB/s (est.)	600 GB/s (B1/B2)	3.35 TB/s
TDP	~400W (est.)	300-400W	700W
Mass production	April 2026 (full production)	Nov 2022	Mar 2022

Key upgrades:

• ✅ 3× compute: from 910B's 256 TFLOPS to 800 TFLOPS
• ✅ Mature software ecosystem: torch_npu adapts PyTorch, MindSpore framework mature
• ✅ Cluster stability: 1,000 cards trained continuously with no failures (the biggest breakthrough)

Technical challenges and solutions​

Challenge 1: Memory demand of trillion-scale models​

A 1.6-trillion-parameter model needs, just for model parameters:

• FP16: 1.6T × 2 bytes = 3.2 TB
• Plus gradients and optimizer states: at least 10 TB of memory

Huawei's solution:

• Model Parallel: distribute the model across 1,000 910C chips
• ZeRO optimizer: optimize memory footprint
• Gradient accumulation: update parameters in stages

Challenge 2: Communication efficiency of thousand-card clusters​

Training with 1,000 chips, inter-chip communication becomes the bottleneck. MoE models need All-to-All communication (each expert may need to communicate with all others).

Huawei's solution:

• HCCS (Huawei Collective Communication Scheduler): in-house high-speed interconnect protocol
• Layered communication: intra-node NVLink + inter-node HCCS
• Communication-compute overlap: data transfer concurrent with computation

Challenge 3: Training stability​

Trillion-scale model training takes weeks or months; any single card failure can interrupt the entire training.

Huawei's solution:

• Fault detection and auto-recovery: real-time monitoring of card status, auto-restart and recovery on failure
• Checkpoint optimization: high-frequency training-state saves (every N steps)
• Ascend cluster management software: designed specifically for enterprise training

Competitive comparison​

Vendor	Chip	1.6T-param training	Ecosystem maturity	Availability
Huawei	Ascend 910C	✅ Completed	⭐⭐⭐ (improving)	China-localized
NVIDIA	H100/H200	✅ Industry standard	⭐⭐⭐⭐⭐	Global (export-controlled)
AMD	MI300X	✅ Feasible	⭐⭐⭐⭐	Global
Google	TPU v5p/8t	✅ JAX-native	⭐⭐⭐⭐	Google Cloud

Conclusion: Ascend 910C has caught up to H100 in hardware performance, still lags in software ecosystem, but this training success proves engineering feasibility.

Industry impact​

1. The "Zunyi Conference" of domestic compute​

This breakthrough is called the "Zunyi Conference" of domestic compute — from passive defense to strategic counteroffensive.

Specific impact:

• ✅ Breaks the bias that "domestic chips can only do inference"
• ✅ Proves domestic chips can train frontier models
• ✅ Provides compute foundation for domestic large models (e.g., DeepSeek-V4, ERNIE 5.0)

2. Impact on NVIDIA​

Huawei Ascend 910C completing trillion-scale training means China's AI industry is less dependent on NVIDIA.

Scenario	Before	Now
Inference	Domestic chips usable	Domestic chips useful
Training	Must use H100/H200	Can use 910C
Large-scale training	Must use H100 clusters	Can use 910C clusters

3. Boost to the domestic chip industry​

This breakthrough will drive the entire domestic AI chip supply chain:

• Chip design: Cambricon, MetaX, Moore Threads accelerate iteration
• Wafer manufacturing: SMIC, Hua Hong get more orders
• Packaging/test: JCET, TFME benefit

Huawei Ascend roadmap (2025-2028)​

Time	Chip	Positioning
Q1 2025	Ascend 910C	Flagship training/inference (mass-produced)
Q1 2026	Ascend 950PR	Inference-optimized (~500 TFLOPS BF16)
Q4 2026	Ascend 950DT	Data-center training
Q4 2027	Ascend 960	Next-gen flagship
Q4 2028	Ascend 970	Next-next-gen

Training lessons shared​

The Shenzhen Hetao College team accumulated valuable experience:

✅ Successes​

1. Progressive training: start from small models (7B), gradually scale to 1.6T
2. Mixed-precision training: BF16 main + FP32 gradient accumulation
3. Communication optimization: All-to-All overlap with computation
4. Fault recovery: save checkpoint every 1,000 steps

⚠️ Challenges encountered​

1. Memory fragmentation: severe fragmentation over long training, needs periodic cleanup
2. Communication bottleneck: MoE All-to-All takes 30%+ of training time
3. Software bugs: torch_npu occasional memory leak, needs training process restart

Related chips​

• Huawei Ascend 910C - the chip used in this training
• Huawei Ascend 910B - previous-gen chip
• Huawei Ascend 950PR - next-gen inference chip
• NVIDIA H100 - benchmark product
• NVIDIA H200 - benchmark product (HBM3e upgrade)

References​

• Sina Finance: Huawei Ascend 910C completes DS-V4-Pro training
• Tencent News: Milestone! Ascend 910C completes 1.6-trillion-param model training
• 21IC: Huawei chip completes full-parameter post-training of 1.6T AI model

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This article is compiled from public reports. Salute to the teams at Shenzhen Hetao College, HIT (Shenzhen), and Huawei — you proved the feasibility of China's AI compute with engineering results.