AI Compute Cards Wiki Editorial

据路透社报道，出口管制推高HBM成本，华为、寒武纪等国产AI芯片厂商集体上调价格——正如戴尔CEO所言，"比涨价更糟的是没货"。

路透社爆料：三位知情人士描绘的涨价全景​

据路透社2026年9月10日援引三位知情人士的报道，因出口管制导致HBM成本飙升，华为、寒武纪等中国AI芯片厂商已大幅上调现有及下一代AI处理器的价格。这不是单一产品的调价，而是一轮覆盖多代产品线的系统性涨价。

产品	年初价格	当前价格	涨幅
华为昇腾950DT加速卡	未公开	指示性价格25万元人民币以上（约37255美元）	两个月内报价最多上涨50%
华为昇腾950PR	约6万元/单卡	突破8万元	约30%
华为昇腾910C板卡（老款）	约9万元	11万元以上	—
寒武纪下一代芯片（暂称690）	未公开	未公开	较两个月前上涨20%-30%

其中最引人注目的是昇腾950DT：其指示性价格已调高至25万元人民币以上（约37255美元），两个月内报价最多上涨50%。年初单卡约6万元的昇腾950PR，现已突破8万元；老款昇腾910C板卡也从年初的约9万元涨至11万元以上——连上一代产品都在涨价，说明短缺是全方位的，而非某一型号的局部现象。

寒武纪官方回应与厂商动态​

在涨价消息流传之际，寒武纪董秘办作出回应："不要听信市场消息，一切以官方公告为准。"这一表态既未证实也未否认。据上述报道，寒武纪下一代芯片（暂称690）已重新定价，较两个月前上涨20%-30%。

与此同时，涨价并非华为与寒武纪的"专属"：沐曦、天数智芯亦有类似的涨价动作。也就是说，这轮价格上行已经从头部厂商扩散至更多国产AI芯片公司，成为行业性现象。对采购方而言，"再等等看会不会降"的观望策略，正在面临价格持续上行的反向风险。

涨价根源：HBM短缺与出口管制双重挤压​

这轮涨价的逻辑链条并不复杂，可以拆成三层：

1. 需求侧：AI算力需求持续爆发，国产AI芯片订单饱满，供不应求是常态；
2. 供给侧：全球HBM持续紧缺，高带宽显存作为AI加速卡最关键的物料，产能增量远远跟不上需求增量；
3. 成本侧：出口限制卡住了国产芯片的上游供应，HBM获取成本大幅飙升，直接推高单卡物料成本。

上游成本抬升叠加供不应求，价格上调几乎是必然结果。对厂商而言，涨价既是转嫁成本的被动选择，也是在新的供需格局下重新校准产品定价的主动机会——毕竟在"有货就能卖掉"的市场里，定价权掌握在供给方手中。

戴尔CEO的警告：2027年可能更严重​

需求侧的信号同样值得警惕。戴尔CEO在高盛大会上表态：半导体结构性短缺短期难以缓解，2027年可能更严重；并且留下一句点睛之语——"比涨价更糟的是没货"。

这句话道破了当前AI算力市场的真实状态：价格上行尚可通过预算调整来消化，而拿不到货则直接卡死算力建设进度，延误的是整个AI战略的落地节奏。HBM作为AI加速卡的瓶颈物料，其短缺正在向上传导为加速卡、服务器乃至智算中心建设层面的系统性不确定性。

对采购决策的影响​

对于正在规划AI算力建设的企业来说，这轮涨价潮至少意味着三件事：

• 预算规划要留弹性：单卡成本模型需要动态更新，参考昇腾950PR两个月上涨约30%的斜率，静态预算很容易失真；
• 交期比价格更关键：昇腾910C这类老款产品都在涨价，说明现货稀缺，早锁定意味着早交付、早形成算力；
• 多供应商组合价值凸显：华为、寒武纪、沐曦、天数智芯全线涨价的环境下，国产+海外、多品牌组合的采购策略更有抗风险能力。

小结​

HBM短缺与出口管制双重压力下，国产AI芯片正在经历一轮罕见的全线上调：华为昇腾950DT报价突破25万元（约37255美元）、两个月最多涨50%，昇腾950PR突破8万元，昇腾910C板卡涨至11万元以上，寒武纪下一代芯片690较两个月前上涨20%-30%，沐曦、天数智芯跟进调价。戴尔CEO"2027年可能更严重"的判断提示我们：这场短缺或许不是短期波动，而是未来数年的行业常态。对采购方而言，与其等待价格回落，不如尽早锁定供货。

开盘暴涨188.37%、市值1764.44亿元——燧原科技的科创板首秀，为国产AI芯片的资本化浪潮再添一把火。

首日表现：高开高走​

2026年9月11日，上海燧原科技股份有限公司正式在上海证券交易所科创板挂牌上市，股票代码688801.SH。开盘价410元/股，较发行价暴涨188.37%，市值达到1764.44亿元；盘中股价最高触及468元/股，涨幅超过229%。

对于一家AI芯片公司而言，这样的首日表现并不常见。它反映的是二级市场对国产AI算力标的的稀缺性定价：在AI算力需求爆发、国产替代加速的双重叙事下，能够提供训练+推理完整产品线的芯片公司，几乎是科创板最炙手可热的资产类别。

指标	数值
上市日期	2026年9月11日
股票代码	688801.SH
上市板块	上交所科创板
开盘价	410元/股
开盘涨幅	188.37%
盘中最高价	468元/股（涨幅超229%）
上市初期市值	1764.44亿元
重要股东	腾讯（浮盈超300亿元）

腾讯作为燧原科技的重要股东，在这场上市中浮盈超过300亿元。从早期一路陪跑到科创板敲钟，腾讯对燧原的持续投入，是互联网大厂深度绑定国产AI芯片公司的典型案例，也印证了一级市场对国产算力赛道的长期押注。

产品底色：云燧训练/推理卡与集群方案​

资本故事之外，燧原的产品线是其估值的底色。燧原科技的核心产品围绕"邃思"DTU芯片展开，基于该芯片打造云燧系列训练加速卡与推理加速卡，并延伸出数据中心级集群方案，覆盖从单卡到大规模部署的完整需求链条。

以燧原T21为例，该卡搭载64GB HBM2E显存，面向大模型时代的显存密集型负载。在HBM容量与带宽成为AI加速卡竞争焦点的当下，大容量HBM配置是衡量产品竞争力的硬指标之一。而集群方案的完整度——从单卡、整机到组网调度——则决定了芯片公司能否真正承接云厂商与行业客户的数据中心级订单。

国产AI芯片的集体资本化​

燧原上市并非孤立事件，而是国产AI芯片企业批量登陆资本市场的最新一站。在此之前，板块格局已经初步成形：

公司	上市地/代码
寒武纪	科创板
摩尔线程	科创板
沐曦	科创板（688802.SH）
天数智芯	港股（09903.HK）
燧原科技	科创板（688801.SH，2026年9月11日）

从训练芯片到推理芯片，从GPU路线到GPGPU、DTU等多技术路线，国产AI芯片公司正在以"科创板为主阵地、港股为补充"的格局完成集体资本化。燧原开盘188%的涨幅，某种程度上是市场对整个板块稀缺性与成长性的集中定价——每一个新上市标的，都在为后来者校准估值坐标。

"融资-流片-上市-再投入"的飞轮​

AI芯片是典型的重资产、长周期行业：一次先进制程流片动辄数亿美元级投入（行业内公认的成本结构），大规模量产还需要持续的产能保障与人员扩张。没有持续的资本供给，技术追赶很难维持节奏。

此番IPO募资，燧原将投向研发与产能两个方向：前者保证下一代芯片的技术迭代与追平能力，后者保证规模交付能力。由此，国产AI芯片行业正在形成一个清晰的飞轮：

1. 融资：一级市场资金支撑芯片流片与团队建设；
2. 流片与量产：产品落地，进入云厂商与行业客户供应链；
3. 上市：借助资本市场完成价值发现与再融资通道建设；
4. 再投入：募资投向下一代研发与产能，进一步缩小与海外厂商的差距。

寒武纪、摩尔线程、沐曦、天数智芯与燧原的接连上市，让这个飞轮转得越来越快。资本市场的持续输血，正在成为国产AI芯片追赶进程中不可或缺的助推器。

小结​

燧原科技科创板首日开盘暴涨188.37%、市值1764.44亿元、盘中最高涨幅超229%，腾讯浮盈超300亿元——这既是资本市场对国产AI芯片稀缺标的的热烈回应，也是"融资-流片-上市-再投入"产业飞轮加速运转的缩影。在HBM紧缺与AI算力需求爆发的双重背景下，国产AI芯片的资本化窗口仍在敞开。后续燧原能否将高估值转化为持续的营收与利润，将是检验这场资本盛宴成色的关键。

当全球最大云计算服务商选择与一家手机SoC巨头联手开发定制AI芯片，数据中心算力市场的竞争逻辑正在被改写。

一场跨多代的战略牵手​

当地时间2026年9月8日，高通技术公司与亚马逊AWS正式宣布达成一项跨多代产品的战略合作。双方将围绕大规模AI数据中心展开两个方向的深度协同：其一是联合开发多代定制AI芯片，其二是共同推进高速光互联解决方案，其中明确包含1.6T光连接方案。

这份协议最值得注意的不是"合作"本身，而是"跨多代"三个字。云厂商与芯片供应商之间的合作，通常以单颗芯片的流片项目为单位；而跨多代的框架式合作，意味着双方在芯片定义、迭代节奏、互联演进路线上都建立了长期协同机制。对高通而言，这是其在数据中心AI芯片市场战略布局上获得的、来自全球最大云计算服务商的关键背书。

合作要点一览​

合作维度	具体内容
合作双方	高通技术公司 × 亚马逊AWS
宣布时间	当地时间2026年9月8日
合作性质	跨多代产品的战略合作
定制芯片	面向大规模AI数据中心联合开发多代定制AI芯片
光互联	联合推进高速光互联解决方案，包含1.6T光连接方案

芯片与光互联并举，是这份协议的另一个信号。在超大规模AI集群中，互联带宽早已成为与算力同等重要的瓶颈，1.6T光连接代表的正是下一代集群网络的带宽量级。芯片设计能力与光互联能力的组合输出，让这桩合作超出了单纯的"定制ASIC"范畴。

高通的第二次冲锋​

对高通而言，数据中心并不陌生，但此前的探索主要集中在推理侧。高通此前已推出AI100、AI200、AI250等推理加速卡产品线，试图将自己在低功耗计算、SoC集成上的多年积累迁移到数据中心场景。

产品线	定位	具体规格
AI100	推理加速卡	未公开
AI200	推理加速卡	未公开
AI250	推理加速卡	未公开

从手机SoC转向数据中心AI芯片，是高通的第二次冲锋。第一次冲锋（AI100/AI200/AI250推理卡）走的是标准产品路线；而这一次的不同之处在于：它不再只是卖标准推理卡，而是直接切入头部云厂商的定制芯片供应链——这恰恰是博通（Broadcom）、Marvell等定制芯片玩家长期占据、且利润丰厚的位置。

这个转变的产业逻辑并不难理解。AI推理需求的爆发让云厂商迫切需要"够用、便宜、可定制"的算力方案，而高通在低功耗设计、异构集成上的基因，恰好与推理场景的诉求契合。借助AWS这个锚点客户，高通有望把定制芯片业务从"试水"升级为"主业"。

AWS的双轨算力战略​

AWS是业内少数坚持自研芯片路线的云计算巨头。其Annapurna Labs团队打造了Trainium训练芯片与Inferentia推理芯片两条自研产品线，支撑起自家大规模算力底座，也是AWS在算力成本上对抗NVIDIA溢价的核心筹码。

此番与高通合作，可以视为AWS在"自研 + 外部定制"双轨战略上的进一步加码：

• 自研线：Trainium/Inferentia保证核心架构可控与成本优化；
• 外部定制线：引入高通等外部设计力量，扩充设计带宽与供应链弹性，应对爆发式的AI算力需求。

两条腿走路的本质是风险对冲：自研芯片的迭代周期难以无限压缩，而外部定制伙伴可以在关键代际上补充产能与设计资源。全球最大云厂商选择加码双轨，本身就说明单一供给模式已经无法满足AI算力的需求曲线。

对行业格局的影响​

这笔合作最直接冲击的，是数据中心定制芯片与互联方案的既有格局：

• 对NVIDIA：头部云厂商在旗舰GPU之外扩充定制AI芯片选项，算力采购组合将更加多元，NVIDIA在数据中心市场的议价空间面临新的边际压力；
• 对Marvell、博通：高通携AWS背书进入定制芯片赛道，定制ASIC设计服务的竞争者又多了一家重量级玩家，客户资源与设计人才的争夺将更激烈；
• 对光互联生态：1.6T光连接的联合推进，意味着超大规模集群的互联带宽军备竞赛继续提速，光模块、光引擎、CPO/NPO相关供应链都将受益于这一代际切换。

更长远地看，"云厂商深度参与芯片定义"正在成为AI基础设施的主流范式。当芯片规格越来越贴近具体业务负载，通用GPU与定制ASIC之间的边界会被不断重画。

小结​

高通与AWS的跨多代合作，是"云厂商定制芯片"趋势下的标志性事件：手机SoC巨头以定制芯片+1.6T光互联的组合拳向数据中心发起第二次冲锋，全球最大云厂商则以"自研+外部定制"双轨强化供应链弹性。对NVIDIA、Marvell、博通而言，一个新的强敌已经入场；对整个AI基础设施行业而言，竞争的维度正在从"单点芯片性能"转向"芯片+互联+云"的全栈博弈。这是2026年下半年最值得持续跟踪的合作之一。

This article is based on market analysis published by Bloomberg Intelligence and Bernstein in September 2026 and public reporting; market share and revenue figures are analyst estimates, not official disclosures.

On September 28, two Wall Street reports simultaneously painted a dramatic picture: the balance of market share in China's AI compute market completed an almost total flip within 12 months.

1. The Share Flip: 40% to 8%, Ascend to 50%​

Bernstein's latest forecast:

• NVIDIA's share of the China AI chip market will fall from about 40% to about 8% by the end of this year
• Huawei Ascend rises to nearly 50%
• The immediate trigger: China's September ban on new H20 orders from NVIDIA, which shut the last channel for NVIDIA's return to the Chinese market
• ByteDance, Alibaba, and Tencent have all placed large Ascend orders

On the timeline, this was not a sudden shock but the cumulative result of three years of tightening export controls: NVIDIA's share of the China AI chip market once peaked at 95%; as high-end chips were cut off, Chinese hyperscale cloud providers pivoted wholesale to Huawei and domestic alternatives. Even when Washington allowed H200 sales to China in January 2026, the gears of that shift had already meshed — there was no going back.

2. Ascend 950PR: The "Chinese H200" in Analysts' Eyes​

What underpins this share data is product strength itself:

• The Ascend 950PR entered mass production in March this year, with FP4 compute of up to 2 PFLOPS and 128GB of domestic HBM
• Analysts rate it as roughly on par with the NVIDIA H200
• Huawei's AI chip revenue is expected to reach $12 billion this year, up 60% from $7.5 billion in 2025

For the full specifications of the 950 series, see our earlier in-depth articles: Ascend 950PR/950DT Dual-Configuration Analysis and Ascend 960 Official Launch — the 960 was ready three quarters ahead of schedule, confirming a one-generation-per-year cadence.

3. The Model Side: Chinese Open Models Take the OpenRouter Token Pie​

While chip shares flipped, the model usage data is equally striking (OpenRouter platform statistics):

Metric	Data
DeepSeek token share (June)	16.3%, surpassing Google, Anthropic, and OpenAI individually to rank first
Combined token share of Chinese open-weight models (May)	About 61% (DeepSeek, Qwen, MiniMax, Tencent Hunyuan, etc.)
Weekly token consumption of Chinese models	About 18 trillion, versus about 5.5 trillion for US models — a gap of more than 3x, with the overtake completed within a year
China-US frontier model performance gap (June)	Narrowed to 6%, a historic low (9% in May)

Compute and models form a positive feedback loop: cards that cannot be bought force domestic compute to scale up; scaled-up domestic compute produces cheap tokens; and cheap tokens let Chinese open-source models swallow the bulk of global inference traffic.

4. But the Stock Market Isn't Buying It​

Bloomberg Intelligence pointed out a contradiction in the same period: the valuation discount of the China Tech 8 relative to the US Magnificent Seven has widened to more than 50%, the widest of the year, and BI believes only a "true AI breakthrough" can close it. Year-to-date stock performance: Alibaba about -7%, Tencent about -23%, while US AI infrastructure leaders broadly gained more than 15%.

There are two readings of this divergence: either the market is underestimating China's AI fundamentals, or earnings execution (Alibaba's EPS missed expectations by 17.3% last quarter, Baidu's by 36%) has dragged down the delivery of the AI narrative. For industry observers, the notable point is: the compute-side data (share, revenue, shipments) has moved ahead, while application-side monetization is still on the way.

5. Three Takeaways for Compute Buyers​

1. For deployments in China, the Ascend ecosystem is already the default option. The cost of migrating from CUDA to CANN is one-time, while supply uncertainty is persistent; after the September ban, there is no compliant path to procuring new NVIDIA cards in the Chinese market.
2. Domestic compute "matching the H200" is a watershed. The implicit assumption of domestic substitution used to be "discounted performance, discounted price"; when single-card performance catches up to the H200 generation, procurement decisions return to pure TCO and supply-security calculations — we recommend using the TCO Calculator to put electricity, depreciation, and utilization into the same table.
3. The token cost curve determines the application landscape. Chinese models' 61% share of OpenRouter tokens shows that the chain of compute self-sufficiency leading to token price drops leading to application prosperity has completed its first leg; the next question is whether inference costs can keep falling.

Summary​

From 40% to 8% is not a slogan but a market reshuffle driven jointly by the ban, product strength, and the model ecosystem. For the Chinese market, the mass-production cadence of Ascend 950/960 and the maturity of the CANN ecosystem will determine whether this share can be held; for the global market, the combination of China's compute "internal circulation + open-source models going overseas" is rewriting the geographic distribution of inference traffic.

(Market share and revenue forecasts come from Bernstein / Bloomberg Intelligence analyst reports; actual figures are subject to each company's financial reports.)

This article is based on the MIIT "15th Five-Year" Plan for ICT Industry Development (issued in September 2026) and official interpretations by the People's Post and Telegraph News, The Paper, Huaxia Times, and other outlets.

In early September, the MIIT issued the "15th Five-Year" Plan for ICT Industry Development, drawing a roadmap for the ICT industry over the next five years with 13 major indicators and 26 key tasks. For the AI compute industry, this is the most substantive policy document — we have picked out five hard targets and break down their industry implications one by one.

Target 1: Intelligent Compute from 1,590 to 9,800 EFLOPS, More Than 5x Growth in Five Years​

This is the standout number in the entire plan. For reference:

• As of the end of June 2026, national intelligent compute capacity had reached 2,185 EFLOPS, up 177% year over year — the first half alone overshot the year-end 2025 target (1,590 EFLOPS)
• The country has built 42 10,000-card-class intelligent computing clusters; in July 2026, the first fully domestic 100,000-card-class AI compute cluster, the Sugon 8000, was completed in Zhengzhou
• Huawei's rotating chairman Wang Tao's assessment: super-node clusters of more than 100,000 cards will become basic configuration by 2027

Going from 2,185 to 9,800 means that over the next four years the country must build 3.5 times the current installed base of intelligent computing facilities. The plan also calls for "orderly deployment of 10,000-card, 100,000-card and larger intelligent computing clusters" and "stepping up efforts to adapt domestic compute chips" — this is the most certain demand base for domestic AI chips over the next five years.

Target 2: Cumulative Information Infrastructure Investment of RMB 3.8 Trillion​

Some have compared this with the "14th Five-Year" figure of RMB 3.7 trillion and concluded that "investment has peaked." Official interpretations explicitly reject this claim: incremental capital is shifting from "scale expansion" to "quality-and-efficiency gains," precisely targeted at intelligent computing infrastructure, 10G optical networks, 6G, and other new tracks. The industry chain pull effect is changing accordingly — AI servers, high-speed optical interconnects, domestic compute chips, and new smart terminals were named as beneficiaries across the whole chain.

Target 3: PUE of New Large Compute Facilities Reduced Below 1.2​

At the end of the "14th Five-Year" period this figure was 1.25, and it must fall another 0.05 within five years — it doesn't sound like much, but with AI servers running at high load year-round and per-rack power density generally exceeding 20kW, every point of PUE reduction is a hard fight. The technical path laid out in the plan is very clear: liquid cooling.

• The "15th Five-Year" Plan for ICT Industry Development: guide compute facilities to adopt high-efficiency energy-saving equipment and advanced technologies such as liquid cooling
• The "15th Five-Year" Plan for Electronic Information Manufacturing Development (jointly issued by the MIIT and the NDRC on September 15): lists liquid cooling alongside high-bandwidth memory pooling and all-optical switching as key technologies to be broken through

Industry-side data confirms the trend: according to Omdia, liquid cooling's share of the global data center cooling market climbed from about 20% in 2024 to about 37% in 2025, with penetration expected to exceed 45% by 2029. The ceiling on compute expansion is shifting from chip supply to power supply, and the energy-efficiency constraint of "compute up, energy down" will be the norm for the next five years.

Target 4: Advanced Storage Capacity of 1,700 EB, More Than 2x Growth​

While intelligent compute grows 5x, advanced storage grows more than 2x — storage-compute coordination is given equal weight. The logic: training checkpoints for large models, and the intermediate states and contextual memory of agent inference, are all stored in layers within high-performance storage. As of the end of June, national storage capacity totaled about 2,021 EB, of which advanced storage accounted for about 32%; the 1,700 EB advanced storage target for 2030 means structural upgrading matters more than total-volume growth.

A direct implication for chip selection: KV cache and long context are eating the memory budget — when evaluating AI servers, memory capacity and memory bandwidth should carry more weight than peak compute.

Target 5: The Agent Interconnection Network Enters the Plan for the First Time​

This is the most forward-looking part of the plan: the "agent interconnection network" gets its own dedicated column, deploying four areas of work — building an agent network identifier system, accelerating the construction and application of agent network infrastructure, promoting global interconnection, and establishing a space governance system. It also explicitly states "launching 6G commercial use in a timely manner."

As AI shifts from "applications for people" to "agent infrastructure," the role of the communications network upgrades from connecting people to connecting agents — providing a national-level narrative for the distributed deployment of inference compute (edge inference, compute scheduling).

Three Judgments for Compute Practitioners​

Judgment	Basis
Domestic compute demand is highly certain	The plan explicitly states "stepping up efforts to adapt domestic compute chips" + the 100,000-card cluster build cycle has begun
Energy-efficiency targets become hard siting constraints	PUE below 1.2 + liquid cooling named as a key technology; high-density liquid cooling solutions take priority
Inference compute sinks to the edge on demand	"Deploy inference compute facilities as needed for scenarios"; edge and regional compute centers enjoy a policy window

Under a 5x compute expansion target, what has always been scarce is not planning but chips, power, and delivery capability. For buyers, the supply window remains tight; for solution selection, we recommend using the TCO Calculator to convert PUE differences into electricity costs — the gap between 1.25 and 1.2 amounts to tens of millions on the electricity bill of a 10,000-card cluster.

Summary​

The "15th Five-Year" Plan writes intelligent compute into a national-level project: 5x compute, 2x storage, RMB 3.8 trillion in investment, PUE 1.2, and the agent internet. Looking back five years from now, the wave of domestic 100,000-card clusters in the second half of 2026 may well prove to be the starting point of this curve.

(Plan data is cited from MIIT documents and official media interpretations; market data is cited from statistics by CAICT, Omdia, and other institutions.)

This article is based on NVIDIA official product pages, the March 2026 GTC architecture blog, and third-party benchmark data; performance figures are vendor architecture comparisons, and actual gains should be verified with your own tests.

NVIDIA has confirmed that Groq 3 LPX — the "seventh chip" of the Vera Rubin platform — has entered full mass production, manufactured at Samsung's Pyeongtaek campus. This is the first time the deal has landed in the form of production silicon since December 2025, when NVIDIA spent roughly $20 billion to obtain a non-exclusive IP license to Groq plus its core engineering team.

For the inference hardware landscape, this is a paradigm-level event: for the first time, NVIDIA has incorporated a "specialized inference architecture defined by someone else" into its own flagship platform — and not as an add-on sale, but as deep co-design.

1. The Groq 3 LPU Chip and the LPX Rack: Specs at a Glance​

Single Groq 3 LPU (4nm, Samsung foundry):

Item	Value
Compiler-managed on-chip SRAM	500 MB
SRAM bandwidth	150 TB/s
Chip-to-chip scale-up bandwidth	2.5 TB/s (96 chip-to-chip links, 112 Gbps each)

A single LPX rack (32 1U liquid-cooled trays, 8 LPUs per tray):

Item	Value
Total LPUs	256
FP8 compute	315 PFLOPS
Total on-chip SRAM	128 GB
Aggregate SRAM bandwidth	40 PB/s
In-rack scale-up bandwidth	640 TB/s
DDR5 memory	12 TB (hosting large model weights)

The 500 MB of SRAM per LPU may not look like much, but multiplied by 256 LPUs and stacked with 40 PB/s of aggregate bandwidth, it forms the physical foundation of "deterministic low-latency decoding" — the LPU's design philosophy is precisely to use compiler static scheduling of on-chip SRAM to completely eliminate memory-fetch stalls during the inference decoding phase, which is exactly the most typical bottleneck of GPU inference.

2. AFD: Attention and FFN Split Up, GPU and LPU Each Do Their Own Job​

LPX does not replace the GPU; instead, it forms a heterogeneous system with Vera Rubin NVL72, centered on AFD (Attention-FFN Disaggregation):

1. Rubin GPUs handle prefill and attention — building the KV cache over large contexts and executing attention layers, consuming HBM capacity and high throughput;
2. Groq 3 LPUs handle FFN / MoE expert-layer decoding — latency-sensitive and pattern-predictable, exactly the home turf of deterministic SRAM scheduling;
3. Intermediate activations are exchanged between the two engines token by token, orchestrated and routed by NVIDIA Dynamo: the GPU computes every attention layer, the LPU computes every feed-forward layer, jointly producing each output token.

The logic of this division of labor is clear: agentic AI applications can consume 15x the tokens of traditional AI applications, and the bottleneck shifts from "can it finish computing" to "can it keep emitting tokens at stable low latency." Let the big HBM container run attention, and let the deterministic SRAM engine run decode — each plays to its strengths.

3. Measured Results and Official Figures​

• Third-party benchmarks (Artificial Analysis): with Gemma 4 31B at a 100K token context, LPX output reaches roughly 3400 tokens/s — inter-token intervals below 1 millisecond, a qualitative leap in interactivity for long-context agentic scenarios
• Official architecture comparisons: with LPX added, Vera Rubin NVL72 achieves up to 35x higher throughput per megawatt on trillion-parameter models; up to 10x more revenue opportunity per watt in "high-value token" scenarios
• Launch customers: Nebius is the first to deploy LPX racks to expand its token capacity; CoreWeave already connects Vera Rubin racks in production with Spectrum-X Multiplane

It must be emphasized: the 35x/10x figures are architecture comparisons at specific high-interaction operating points, not universal conclusions. For training, high-throughput batch inference, and workloads that need CUDA ecosystem flexibility, the GPU remains the right answer; LPX's home turf is scenarios where "single-user interactive latency is the product" — agent loops, real-time coding assistants, long-context conversations.

4. Three Industry Signals​

1. Specialized inference chips get absorbed, not opposed. The old narrative of the LPU as a "GPU challenger" has become part of Vera Rubin. The endgame for inference hardware may not be one architecture winning, but the heterogeneous combination of "GPU + specialized decoding engines" becoming the standard. For other inference chip startups (Cerebras, Etched, etc.), this is both proof that the ceiling has risen and a warning: get integrated or find differentiation.

2. Samsung foundry lands a high-end AI order. Against the backdrop of TSMC's near-monopoly on AI main chips, Samsung 4nm taking on LPX mass production is highly significant — combined with Tesla's earlier AI6 2nm order, Samsung foundry has a shot at returning to full-year profitability in 2027.

3. Inference economics enters the "priced per MW" era. When vendors start telling their story with tokens/MW and revenue per watt, the core KPI of compute selection has completely shifted from peak compute (TFLOPS) to token output per unit of energy. This is consistent with the power-and-electricity cost model built into our TCO Calculator: the chip with the best-looking peak specs is not necessarily the chip with the lowest cost per token.

Summary​

Groq 3 LPX mass production marks the arrival of a heterogeneous era for inference hardware: "GPUs manage throughput, LPUs manage latency." For teams currently selecting inference clusters, the recommendation is to evaluate workloads separately: keep batch offline inference on GPUs, and separately calculate the unit cost of LPX-class solutions for interactive long-context agents. If in doubt, run the 3-year total cost of ownership of both architectures through the TCO Calculator before deciding.

(Performance data in this article comes from NVIDIA official architecture comparisons and Artificial Analysis third-party benchmarks; for actual deployments, please rely on your own testing.)

According to ZhiXun (media) reporting in late September, Nebius announced that on-demand rates for H100 / H200 / B200 will rise by an average of about 20% starting October 1. The same month, Cailian Press reported that as of August 11 CoreWeave's contracted power had grown to 4.2 GW and that it would "keep signing new compute at higher prices". This is the Nth consecutive price increase in the rental market this AI cycle — and for buyers, the TCO balance between building and renting is shifting. This article works through the math using the site's TCO calculator methodology.

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1. Three Forces Behind the Price Hikes​

• Exploding agentic inference demand: from MLPerf v6.1 to SemiAnalysis AgentX, agentic workloads have become the main engine of inference growth — token consumption is orders of magnitude beyond chat scenarios, and inference compute has gone from "enough" to "never enough";
• Supply premium on the new platform generation: Vera Rubin NVL72 has debuted on CoreWeave, and early-ramp pricing on new platforms is naturally elevated — which also raises the anchor for renewal prices on the previous generation (H100/H200/B200);
• Power has become a hard constraint: CoreWeave's 4.2GW of contracted power shows the data center supply bottleneck has shifted from GPUs to power and racks; enterprises holding power contracts have no reason to cut prices.

2. What a 20% Rent Increase Means for TCO​

The site's TCO calculator splits total cost of ownership into five parts: purchase + energy + operations + network + discounting. Rent increases don't enter that model directly, but they change the "rental baseline" — the opportunity cost a build option must beat:

Scenario	Before 20% Rent Hike	After 20% Hike
Short-term elastic workloads (under 1 year)	Renting wins	Renting still wins (build deployment lead times can't catch up)
Steady inference workloads (2-3 years)	Crossover zone	Build starts to win (opportunity cost rises)
Training clusters (3 years+)	Build wins	Build's advantage widens

Rules of thumb:

• For workloads running 24/7 at full load for 2 years or more, a 20% rent increase is usually enough for building (even at a 1.5x purchase premium and with a PUE 1.3 energy model) to overtake renting within 30 months;
• Tidal workloads (daytime peaks, idle nights) should still rent — under the assumption that a build pays a continuous 15% idle power draw, building almost never breaks even below roughly 50% utilization;
• A hybrid strategy (owned baseline + rented peaks) is least sensitive to rent increases and is the robust play in the current interest-rate and power-price environment.

You can re-derive these conclusions in the TCO calculator: enter the "cloud rental unit price" at +20% and compare scenarios across purchase price, electricity price, and PUE. The default discount rate is 8%; purchase costs are not discounted, and annual electricity is discounted by 1.08^-y.

3. Pricing Implications for Domestic Compute​

Rent increases have a layer of impact on domestic AI chip purchasing decisions that is easy to overlook:

• The rental market for domestic chips is not yet mature: compute from Ascend / Cambricon / Moore Threads is delivered mostly as appliances, full racks, and intelligent computing center allocations; public on-demand rental prices are scarce — so procurement comparisons naturally lean toward "build / full-system" models;
• Relative TCO shift: a 20% NVIDIA rent increase raises the "relative attractiveness" of every domestic alternative, especially for inference workloads (actual market transaction prices for 910C / 950PR / P800 on the primary market are not public, but the full-system price gap versus dollar-priced cards is widening);
• Supply cadence: DeepSeek betting on Ascend training and rumors of 160,000-unit 950DT purchases — top demand eats capacity first, and queue times for later buyers are lengthening. Deciding early has value in itself.

4. Takeaways​

• Nebius raises H100/H200/B200 on-demand rates +20% from October; CoreWeave's contracted power at 4.2GW keeps locking in volume at high prices — rental market supply and demand remain tight;
• Agentic inference + Rubin supply premium + power constraints: three forces pushing rents up, with no near-term reversal in sight;
• Decision framework: steady workloads 2 years+ → the build window opens; tidal workloads → keep renting; hybrid strategies are most price-hike resistant;
• What to watch: whether other clouds follow with price moves, formal Rubin rental pricing, and whether a public rental market for domestic compute emerges.

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Further Reading​

• TCO Calculator (this site's interactive tool, full parameters for purchase / energy / discounting)
• Vera Rubin NVL72 MLPerf v6.1 Debut
• DeepSeek Confirms Bet on Huawei Chips for Large-Model Training

References​

• ZhiXun (media): Nebius raises AI chip rental prices; from October 1, H100/H200/B200 on-demand rates rise about 20% on average (2026-09-21)
• Cailian Press / East Money: CoreWeave deploys multi-rack Vera Rubin NVL72 cluster, contracted power grows to 4.2 GW (2026-09)

This article is compiled from public reports; TCO conclusions depend on assumptions such as utilization, electricity price, and discount rate. Please re-compute with your own parameters using the TCO calculator.

On September 22, 2026, multiple media outlets reported that DeepSeek's CEO explicitly stated the company is betting heavily on Huawei chips, expects to receive a new batch of Huawei chips for large-model training, and stressed that "this choice must succeed." Following earlier reports that "DeepSeek planned to procure 160,000 Ascend 950DT units for inference," this is the most significant alignment signal yet in the domestic compute ecosystem — an upgrade from inference procurement to a training bet.

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1. The Signal Chain: Four Steps to a "Training Bet"​

Piecing together the public information from the past six months, the DeepSeek–Ascend collaboration shows a clear escalation path:

Time	Signal	Nature
Mid-2026	DeepSeek V4 completes ecosystem migration from CUDA to CANN	Software adaptation
August 2026	Report: DeepSeek plans to procure 160,000 Ascend 950DT units for inference deployment	Inference procurement intent
2026-09-17	HC2026: 960DT ready three quarters ahead of schedule, 950DT ramping in Q4	Supply delivery
2026-09-22	DeepSeek CEO: betting on Huawei chips for LLM training, "must succeed"	Training bet

The key change is the workload tier: inference deployment means "cutting costs with off-the-shelf compute," while a training bet means "staking the existence of next-generation models on domestic chips" — training clusters demand an order of magnitude more in stability, interconnect efficiency, and software-stack maturity.

2. Huawei's Ability to Deliver​

DeepSeek's willingness to commit rests on a series of verifiable progress points on Huawei's supply side (all official figures):

• One generation per year, delivered: the 950PR is in mass production, the 950DT ramps in 2026 Q4, and the 960DT moved three quarters earlier than its original 2027 Q4 plan to ready in 2027 Q1 / launch in Q2 — the roadmap's credibility validated twice in a row;
• Deployment scale: Ascend supernodes have been commercially deployed at scale in over 1,000 sets, covering internet, finance, healthcare, and manufacturing;
• Ecosystem maturity: CANN has entered routine open-source operation, with external developers exceeding 61% for the first time and 5,200 monthly active developers; there are over 40 Ascend-native training models, making it the only domestic technology route supporting pretraining;
• Training evidence chain: China Telecom's Xing 4.0-29B-A4B agentic MoE model, open-sourced in September, was announced as trained end-to-end on Ascend (company claim) — "Ascend can train large models" is no longer just Huawei's self-attestation.

See the Ascend 950DT and Ascend 960 spec pages for details; for supernode analysis, see Ascend 960 Official Launch.

3. Why DeepSeek?​

DeepSeek's choice has strong structural drivers:

1. Supply certainty: under export-control constraints, NVIDIA's flagship supply to China keeps tightening; domestic compute is the only plannable large-scale training supply;
2. Cost structure: DeepSeek has always been known for extreme engineering efficiency (the V3 training cost set the industry benchmark), and domestic compute plus supernode system efficiency fits its approach;
3. Betting on ecosystem dividends: CANN open-sourcing plus deep binding with leading model vendors means model vendors can participate in shaping the toolchain's direction — something impossible within CUDA's closed system;
4. Self-fulfilling demonstration effect: a leading lab's public commitment pulls back on Huawei's production scheduling and upstream HBM and system investment, making "must succeed" a rational commitment rather than a slogan.

4. Risks and Open Questions​

Viewed coolly, this route still has three items that need time to verify:

• Actual training scale: the quantity, model type (950DT or 960DT), and delivery schedule of the new batch of chips are all undisclosed;
• MFU methodology: the MFU / latency gains Huawei cites all come from Markov-lab simulations, with no independent third-party measurements yet; the real effective compute of a training cluster depends on long-term data from large-scale production environments;
• Per-card generation gap: the 960DT's 4 PFLOPS (FP4) versus Rubin R200's 50 PFLOPS (FP4) — the per-card gap objectively exists, and training efficiency depends on whether supernode scale and software optimization can compensate; that is precisely the decisive battleground of "system-level competition."

5. Summary​

• DeepSeek confirms betting on Huawei chips for training large models — the first training-grade commitment from a leading lab in domestic compute;
• Signal chain: CUDA→CANN migration → 160,000-unit 950DT inference procurement rumor → 960 ready ahead of schedule → training bet;
• Supporting factors: one-generation-per-year delivery, 1,000+ supernode sets, and 61% external developers in the CANN open-source ecosystem;
• What to watch: actual arrival of the new chips and training-cluster scale, third-party MFU data, and training-compute disclosure in DeepSeek's next release.

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Further Reading​

• Ascend 960 spec page / Ascend 950DT spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%
• Alibaba Zhenwu V900 Unveiled at Apsara Conference

References​

• Toutiao Tech Morning Report: DeepSeek confirms betting on Huawei chips for large-model training (2026-09-22)
• HUAWEI CONNECT 2026 official announcements (2026-09-17)
• Earlier report: DeepSeek plans to procure 160,000 Ascend 950DT units (2026-08)

This article is compiled from public reports and vendors' official statements. Details such as chip quantities and training-cluster scale are subject to subsequent disclosures from DeepSeek and Huawei.

Beyond the official Ascend 960 unveiling and the Zhenwu V900 launch, late September also delivered three ecosystem signals that headline coverage easily drowned out, yet whose structural significance rivals flagship chips: a carrier open-sourcing a model trained on Ascend, an OEM delivering a hundred-chip-class domestic inference system, and a cloud-compute chip startup closing a new funding round. This article breaks down each one.

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1. China Telecom Open-Sources Xing4.0: Carrier-Grade Endorsement for End-to-End Ascend Training​

On September 23 (as reported), China Telecom open-sourced Xing4.0-29B-A4B — an agentic mixture-of-experts (MoE) model that the company says was trained end-to-end on Huawei Ascend accelerators.

Why it matters:

• Third-party proof that "it can train": until now, evidence that "Ascend can train large models" came mainly from Huawei itself (40+ natively trained models); a carrier running training with its own data, engineering teams, and clusters — and open-sourcing it — is the first scaled training case outside the Huawei ecosystem;
• Agentic positioning: the 29B-A4B (29B total / 4B active) MoE form factor targets agent workloads directly — aligned with the open-source cadence of DeepSeek and Qwen, rather than a small experimental model;
• Open-source spillover: publishing model weights plus the training recipe means Ascend training engineering know-how can be reused by other institutions — the standard playbook for ecosystem diffusion.

Combined with Huawei's disclosure that "CANN has entered routine open-source operations, with external developers at 61%", the Ascend ecosystem is shifting from "vendor-led" to "community-operated".

2. Inspur MetaBrain SD200 Ultra: Measured Throughput Claims for a 128-Chip Domestic Inference System​

Inspur launched the MetaBrain SD200 Ultra inference system around the same time:

Metric	Value (company figures)
Domestic AI chips	128 chips (vendor did not disclose specific models)
Model served	Kimi K3
Token throughput	2.8T tokens (system throughput figure under that methodology)
Latency	5.85 ms

Three readings:

• Hundred-chip-class system integration: 128 chips cooperating across a heterogeneous setup to run very large MoE inference is a test of interconnect topology, scheduling, and fault tolerance — OEMs are now demonstrably capable of assembling domestic chips into large systems;
• Aimed at top open-source models: targeting Kimi K3 (already live on AWS Bedrock) as the benchmark workload shows the acceptance standard for domestic inference systems is "runs today's most popular models", not a self-referential demo;
• Mind the methodology: the 2.8T token throughput and 5.85ms latency are both vendor claims; the tested model version, concurrency, and batch size were not disclosed, so procurement evaluations should re-test under real workloads.

3. EVAS Closes RMB 2 Billion B+ Round: The Cloud Compute Chip Race Still Attracts Capital​

EVAS (Yixing Intelligence) completed a B+ round of RMB 2 billion, at a post-money valuation near RMB 15 billion, with Oriza Capital following on; earlier in the first half of the year it had closed a RMB 1.5 billion Series B and brought in China Mobile as a strategic investor. The company focuses on next-generation cloud compute chips.

In 2026, when the flagship chip lineup (Ascend / Cambricon / Moore Threads / Hygon / Zhenwu) looks settled, a cloud compute chip newcomer still raising RMB 2 billion suggests:

• Primary-market conviction in the "second tier of domestic compute": with top vendors' capacity booked into 2027, overflow demand gives newcomers a window;
• The role of carrier strategic investment: China Mobile is both a buyer and an investor — the demand side of domestic compute is using capital to lock in the supply side;
• Differentiated room remains for cloud inference DSA routes (see the ecosystem positioning of routes like Tsingmicro and Houmo).

4. Assembling the Week's Signals: The Loop Is Taking Shape​

Put the three signals together with this month's flagship launches, and every segment of the domestic compute loop now has players filling the gaps:

Segment	This Month's Evidence
Flagship chips	Ascend 960 early official unveiling (9-17), Zhenwu V900 launch (9-22)
Training validation	China Telecom's Xing4.0 end-to-end trained on Ascend and open-sourced, DeepSeek betting on Ascend training
Inference systems	Inspur SD200 Ultra running Kimi K3 on 128 chips
Software ecosystem	CANN routine open-sourcing, external developers at 61%
Capital supply	EVAS B+ round of RMB 2 billion (post-money near RMB 15 billion)
Demand side	DeepSeek's alignment, Kimi K3 live on overseas cloud platforms

Independent players are investing across all four segments — "chips, systems, models, capital" — the biggest difference from the "isolated breakthroughs" of 2024-2025.

5. Takeaways​

• China Telecom Xing4.0-29B: the first open-source model end-to-end trained on Ascend outside the Huawei ecosystem;
• Inspur SD200 Ultra: a 128-chip domestic inference system at 2.8T token throughput / 5.85ms (company figures, pending re-testing);
• EVAS RMB 2 billion B+ round: the cloud compute chip second tier is still getting real money;
• What to watch: Xing4.0's training cluster scale and MFU, third-party re-tests of the SD200 Ultra, and EVAS's tape-out cadence.

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Further Reading​

• Ascend 960 Spec Page / Ascend 910C Spec Page (this site)
• DeepSeek Confirms Bet on Huawei Chips for Large-Model Training
• Domestic Top Three in 2026 H2: Localization Rate Breaks 40% and Marches Toward 60%

References​

• The GPU Daily (2026-09-24): China Telecom open-sources Xing4.0-29B; Inspur MetaBrain SD200 Ultra
• Toutiao (2026-09-21): EVAS completes RMB 2 billion B+ round, post-money valuation near RMB 15 billion
• CSDN AI Daily (2026-09-21): Huawei CANN enters routine open-source operations, OceanStor M900 launched

This article is compiled from public reports. Xing4.0 training details and SD200 Ultra performance figures are company statements; testing conditions are subject to subsequent disclosures.

Just five days after Huawei officially announced the Ascend 960 at HUAWEI CONNECT on September 17, Alibaba unveiled its new unified training-and-inference AI chip, Zhenwu V900, at the Apsara Conference in Hangzhou on September 22 — which Alibaba calls "the most powerful Chinese self-developed AI chip in terms of compute performance to date." This article is compiled from Alibaba's official announcements and reports from Sina Tech, C114, Huanqiu.com, and other sources.

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1. Single Chip: 3x M890, 216GB + 1200GB/s​

Metric	Zhenwu V900 (this launch)	Zhenwu M890 (previous generation)
Performance	3x Zhenwu M890 (official figure; absolute value undisclosed)	FP16 600 TFLOPS (as catalogued on this site)
Memory	216 GB	144 GB (HBM3)
Chip-to-chip interconnect	1200 GB/s	—
Precision	Native FP8 / FP4 (including high-precision training)	—
Positioning	Unified training and inference (trillion-parameter-scale training + low-precision inference)	Unified training and inference
Mass production	2027 Q1, scaled deployment in Alibaba Cloud data centers	Already deployed at scale

Three takeaways:

• Memory crosses into the 200GB+ tier: 216GB puts it in the same capacity class as the Ascend 960DT (288GB self-developed HBM) and NVIDIA Rubin (288GB HBM4), leveling the capacity threshold for long-context and very large MoE models;
• 1200GB/s chip-to-chip interconnect: laying the foundation for the supernode's "memory-semantics interconnect" — the chip-level prerequisite that pairs with ICN Switch;
• Precision coverage across all scenarios: officially described as "high-precision training, low-precision and ultra-low-precision inference across all scenarios," with native FP8/FP4 support aligned with the common spec of 2026's new cards.

The absolute single-chip compute figure has not been officially disclosed; this site records it using the official relative figure of "3x M890." See the Zhenwu M890 spec page for M890 details.

2. System Level: ICN Switch + Panjiu Supernode, a 500,000-Card Single Cluster​

V900's real selling point is not the single chip but system-level collaboration:

• ICN Switch self-developed interconnect chip: once connected, the supernode gains native memory semantics and unified memory addressing, with a thousand cards interconnected at full bandwidth — over a thousand V900s can "work together like a single super chip";
• Panjiu supernode server: integrates V900 (compute) + ICN Switch (interconnect) + Panmai intelligent NIC (network) + Zhenyue SSD controller (storage), a fully self-developed compute-storage-network stack;
• 500,000-card single cluster: combined with Alibaba Cloud's next-generation intelligent computing center network architecture, a single cluster can scale up to 500,000 cards.

This mirrors Huawei's "11 key chips" approach: the unit of competition has shifted from the single chip to whole-system delivery capability — Zhenwu handles compute, Yitian handles general-purpose computing, Panmai handles networking, Zhenyue handles storage, and ICN Switch handles interconnect.

3. Business and Roadmap​

• The Zhenwu family has served over 650+ enterprise customers (as of June 2026), spanning autonomous driving, finance, large models, embodied AI, energy, and manufacturing;
• Supernodes based on the M890 are already deployed at scale, running models with over 2 trillion parameters such as Qwen3.8 and Kimi K3; Alibaba Cloud will add new serving nodes in Q4 to expand supernode supply;
• Roadmap: V900 enters mass production and sales in 2027 Q1; Zhenwu J900 is planned for release in 2027 Q3;
• CPU synergy: Yitian 720 / 730 arrive in 2027 (the 730 is the first to adopt T-Head's fully self-developed CPU microarchitecture, with single-core SPECint2017/GHz up to 1.4x that of Yitian 710); the 2029 Yitian 750 will interconnect directly with Zhenwu AI chips via the ICN bus;
• Alibaba Group CEO Eddie Wu said T-Head's AI chip annual shipment volume will increase substantially.

4. Competitive Coordinates: Two Swords in One Week​

Viewing the two mid-September launches side by side, the landscape of "system-level competition" among domestic AI chips is now clear:

Dimension	Huawei Ascend 960 (9-17)	Alibaba Zhenwu V900 (9-22)
Launch event	HC2026	Apsara Conference 2026
Per-card memory	288GB (self-developed HBM)	216GB
Memory bandwidth	9.6 TB/s	Undisclosed
Interconnect	LinJu UnifiedBus / NPO optical interconnect	ICN Switch memory-semantics interconnect
Supernode	Ascend 960 supernode (4,096 cards, 8 EFLOPS FP8)	Panjiu supernode (500,000-card single cluster)
Availability	2027 Q2	2027 Q1

Huawei is taking the "supernode + open-source CANN ecosystem" route, while Alibaba is taking the "full cloud stack + open-source model ecosystem" route; both still trail in per-card specs, but what they deliver are procurable, operable ultra-large-scale clusters. The substitution logic against NVIDIA's CUDA ecosystem is shifting from "performance parity" to "supply certainty + system efficiency."

5. Summary​

• V900: 3x M890, 216GB, 1200GB/s chip-to-chip interconnect, native FP8/FP4, mass production in 2027 Q1;
• System: ICN Switch with thousand-card full bandwidth, Panjiu supernode with a fully self-developed compute-storage-network stack, 500,000-card single cluster;
• Cadence: J900 in 2027 Q3, Yitian 730 in 2027, Yitian 750 in 2029 — T-Head's first three-year generational roadmap;
• What to watch: actual mass production and Alibaba Cloud deployment scale in 2027 Q1, disclosure of V900's absolute compute, and the possibility of external supply of ICN Switch.

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Further Reading​

• Zhenwu M890 spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%

References​

• Huanqiu.com: T-Head launches new unified training-and-inference AI chip Zhenwu V900 (2026-09-22)
• Sina Tech / TechWeb: Alibaba T-Head launches new AI chip Zhenwu V900, mass production in the first quarter of 2027
• C114: Alibaba launches new AI chip Zhenwu V900, mass production in 2027 Q1

This article is compiled from Alibaba's official announcements and public reports. The absolute single-chip compute of V900 has not been officially disclosed; supernode and cluster scale figures are official claims, subject to actual future delivery.