2 posts tagged with "Ascend 910C"

June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

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2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

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3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

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4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

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5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

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Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

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Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

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References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

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This article is continuously updated. Please provide the latest developments.

Huawei Ascend 910C (Ascend 910C), Huawei's third-generation Ascend AI chip, adopts innovative dual-die (Chiplet) packaging and began mass supply in May 2025, becoming the backbone of domestic AI compute.

This article comprehensively analyzes this domestic flagship AI chip across four dimensions: technical specs, deployment cases, performance comparison, and market positioning.

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1. Core Technical Specifications​

1.1 Chip architecture and process​

Item	Parameter
Architecture	Da Vinci (dual-die packaging)
Process	SMIC N+2 (7nm-class)
Packaging	Chiplet (2× Ascend 910B compute dies)
Transistors	~53 billion
Die size	~800mm² (estimated)

Technology highlights:

• Dual-die Chiplet packaging integrates two 910B chips, breaking the single-die yield bottleneck
• Centerless I/O die design lets the two compute dies interconnect directly, reducing communication latency
• SMIC N+2 process delivers 7nm-class performance with a controllable, autonomous supply chain

1.2 Compute performance​

Precision	Compute	Reference
BF16	800 TFLOPS	~60% of NVIDIA H100
FP16	~800 TFLOPS	Close to H100 at same precision
INT8	~1600 TOPS	Clear inference advantage
FP32	Not disclosed	Training mainly uses BF16/FP16

Performance characteristics:

• 800 TFLOPS at BF16, a new domestic AI chip compute benchmark
• ~2× compute over 910B (dual-die stacking + architecture optimization)
• No FP8 precision support (NVIDIA Blackwell's strength)

1.3 Memory and interconnect​

Item	Parameter
HBM type	HBM2E (8 stacks)
Memory capacity	~128 GB (combined dual-die)
Memory bandwidth	784 GB/s
Interconnect protocol	Huawei AscendLink (in-house)
Interconnect bandwidth	400 GB/s unidirectional (800 GB/s bidirectional)

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 784 GB/s is a high-end configuration among HBM2E solutions
• In-house AscendLink protocol supports 384-chip all-optical interconnect

1.4 Power and energy efficiency​

Item	Parameter
TDP (dual-die)	~310 W
Energy efficiency (BF16)	~2.58 TFLOPS/W
vs. H100	~45% of H100's power, comparable energy efficiency

Energy efficiency advantages:

• At equal compute, significantly lower power than NVIDIA H100 (700W)
• 7nm-class process, ~30% better energy efficiency than 910B
• Suited to large-scale cluster deployment, reducing data center PUE pressure

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2. Key Deployment Cases​

2.1 CloudMatrix 384 SuperNode​

System specs:

Item	Configuration
Chip count	384 Ascend 910C
Cabinets	16 (12 compute + 4 network)
Total HBM	~49 TB (128GB × 384)
Interconnect	All-optical mesh network
Optical modules	6,912 LPO optical modules
System BF16 compute	~300 PFLOPS

Performance comparison:

• CloudMatrix 384's total BF16 compute exceeds NVIDIA GB200 NVL72 (72× B200)
• In large-model training, 384-chip 910C linear scaling efficiency reaches 85%+
• Supports smooth scaling to ten-thousand-card clusters for ultra-large training

Deployment progress:

• As of June 2026, over 500 CloudMatrix 384 SuperNodes deployed
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud, iFlytek
• Scenarios: large-model training, smart customer service, autonomous-driving simulation, scientific computing

2.2 DeepSeek-V4-Pro full-parameter post-training​

Breakthrough significance:

On June 5, 2026, the AI training platform of Shenzhen Hetao College — together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and Shenzhen Zhicheng AI Compute Platform — completed full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model on an Ascend 910C compute cluster.

Technical highlights:

• Among the world's first to run full-parameter post-training of a trillion-parameter model on a domestic compute platform
• Validates Ascend 910C maturity in ultra-large-model training
• Proves domestic AI chips now have the capability to replace imported chips

Performance data (official disclosure):

• Training throughput: ~60% of an H100 cluster (BF16 precision)
• Memory utilization: 92% (128GB HBM2E capacity advantage)
• Interconnect efficiency: 384-chip linear scaling efficiency 85%+
• Stability: 30 consecutive days of training with no failures

2.3 Commercial deployment cases​

Case 1: A provincial big-data center (300 P FLOPS compute center)​

• Scale: 300 P FLOPS AI compute (~1,000× 910C)
• Scenarios: government large model, city brain, smart transportation
• Deployment: September 2025
• Investment: ~¥200M (120 servers)

Case 2: Huawei Cloud AI training platform​

• Chips: over 10,000 Ascend 910C
• Customers served: over 500 enterprises
• Model support: Pangu large model, third-party open-source models (LLaMA, ChatGLM, etc.)
• Global deployment: China, Southeast Asia, Middle East, Latin America

Case 3: iFlytek smart education​

• Scale: 256 Ascend 910C
• Scenarios: smart-education large model, speech recognition, machine translation
• Performance: 90% faster training than 910B

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3. Performance Comparison Analysis​

3.1 vs. NVIDIA H100​

Item	Ascend 910C	NVIDIA H100	Notes
BF16 compute	800 TFLOPS	~1,300 TFLOPS	910C ~60% of H100
HBM capacity	128 GB	80 GB	910C +60%
HBM bandwidth	784 GB/s	3.35 TB/s	H100 clear bandwidth lead
TDP	310 W	700 W	910C only 45% of H100 power
Process	7nm (SMIC N+2)	4nm (TSMC)	H100 more advanced
Software ecosystem	CANN (CUDA-compatible)	CUDA	H100 more mature
Supply	China autonomous	Export-controlled	910C no supply-chain risk

Conclusion:

• In raw compute, 910C is ~60% of H100
• In memory capacity, 910C leads by 60%, suited to large-model training
• In energy efficiency, 910C clearly outperforms H100
• In supply chain security, 910C wins outright

3.2 vs. Ascend 910B​

Item	Ascend 910C	Ascend 910B	Improvement
Architecture	Dual-die Chiplet	Single die	—
BF16 compute	800 TFLOPS	~400 TFLOPS	+100%
HBM capacity	128 GB	64 GB	+100%
TDP	310 W	310 W	Flat (single-die power)
Process	SMIC N+2	SMIC N+2	Same
Yield	~40%	~30%	+33%

Conclusion:

• 910C's dual-die packaging doubles compute and memory capacity
• Yield up from 910B's 30% to 40%, lowering manufacturing cost
• At equal power, 100% performance gain, significantly better energy efficiency

3.3 Inference performance (DeepSeek measured)​

Test environment:

• Model: DeepSeek-V3 (671B parameters)
• Hardware: Ascend 910C vs NVIDIA H100
• Precision: BF16
• Batch size: 64

Results:

Metric	Ascend 910C	NVIDIA H100	Ratio
Inference speed (tokens/s)	8,500	14,200	60%
First-token latency (ms)	120	85	141%
Power (W)	310	700	44%
Cost (¥10k/card)	~10	~18	56%

Conclusion:

• 910C inference speed is 60% of H100, but power only 44%
• In cost-sensitive scenarios, 910C's cost-performance advantage is clear
• For China-market localization needs, 910C is the only option

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4. Market Positioning and Competitive Advantages​

4.1 Target markets​

Core markets:

1. Chinese government and SOEs: localization, data security, autonomy
2. Large-model startups: cost-sensitive, high compute demand
3. Operators and cloud providers: large-scale deployment, high efficiency requirements
4. Research and education: ultra-large-scale computing, talent development

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart healthcare: medical imaging, drug discovery
3. Fintech: risk control, robo-advisory

4.2 Competitive advantages​

Advantage	Description
Autonomy	SMIC N+2 process + Huawei in-house architecture, no supply-chain risk
Large memory	128GB HBM2E, full-pipeline training of hundred-billion-parameter models
High energy efficiency	310W TDP delivers 800 TFLOPS, close to H100 efficiency
System scaling	CloudMatrix 384 SuperNode, total compute exceeds GB200 NVL72
Software ecosystem	CANN CUDA-compatible, lower migration cost
Cost advantage	~¥100k/card, ~44% cheaper than H100

4.3 Weaknesses and improvement directions​

Weakness	Improvement direction
Single-chip compute	Next-gen 910D to adopt 3nm, target doubling
HBM bandwidth	950 series to adopt in-house HBM (HiBL 1.0), bandwidth to 4 TB/s
Software ecosystem	Continued CANN + MindSpore investment, expand developer community
Process	Deep cooperation with SMIC to ramp N+3 (5nm-class)

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5. 2026 Shipment Plan and Market Forecast​

5.1 Shipment plan​

Period	Shipments	Cumulative	Key customers
2025 Q2-Q4	200k	200k	Huawei Cloud, China Telecom
2026 Q1-Q2	300k	500k	China Mobile, China Unicom, iFlytek
2026 Q3-Q4	300k	800k	Government projects, large-model startups
2027	1,000k	1,800k	Global market (Southeast Asia, Middle East, Latin America)

Capacity bottleneck:

• SMIC N+2 capacity ~100k wafers/month, Ascend 910C ~30% of that
• 2026 plan of 800k chips needs ~400k wafers, requiring 80%+ utilization
• Huawei prioritizes 910C capacity via deep SMIC cooperation

5.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Ascend 910C share: ~60% (¥10.5B, ~800k chips)

Global AI chip market (2026):

• Total: ~$200B
• Huawei share: ~5% ($10B)
• Growth drivers: China-market localization + Belt and Road exports

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6. Summary and Outlook​

6.1 Core conclusions​

1. Ascend 910C is a milestone domestic AI chip, with comprehensive breakthroughs in compute, memory, energy efficiency, and system scaling
2. CloudMatrix 384 SuperNode proves domestic chips can replace imported ones
3. DeepSeek-V4-Pro training success validates 910C maturity in ultra-large-model training
4. 800k chips shipped in 2026, projected 60% of China's AI chip market

6.2 Future outlook​

Short term (2026-2027):

• 910C continues ramping, shipments exceed 1,000k
• CloudMatrix 384 deployments over 1,000 units
• Software ecosystem (CANN + MindSpore) maturity approaches 70% of CUDA

Medium term (2028-2029):

• Next-gen 910D mass production, 3nm process, target 1.6 PFLOPS BF16
• 950 series (PR/DT) becomes inference-market mainstay, share over 30%
• 960/970 launch, N+3 process, supports trillion-parameter models

Long term (2030+):

• Huawei Ascend series becomes TOP 3 of the global AI chip market
• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"

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References​

1. Huawei Ascend 910C — Baidu Baike
2. Huawei Ascend series AI chip detailed parameter comparison (2025-2028) — EET-China
3. Huawei Ascend 910C compute cluster powers domestic chip's successful trillion-scale AI large-model training — QQ News
4. Huawei Ascend 910C completes DeepSeek V4 Pro training — Huxiu
5. Huawei Ascend 910C measured efficiency surpasses H100, AI Infra software-hardware co-optimization shines at ten-thousand-card cluster — CNBlogs

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Last updated: June 10, 2026