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Hyperscaler Custom Silicon Wave 2026: OpenAI Jalapeno, Maia 200, MTIA, TPU v8 Together "De-NVIDIA-ize"

· 6 min read
Industry Research Team

The Tuesday-afternoon AI session at Hot Chips 2026 this August was the most historically significant of the conference — not because any single chip was so powerful, but because almost everything on stage was a "hyperscaler de-NVIDIA-ization" custom ASIC: Google's 8th-gen TPU, OpenAI's first self-designed chip, Microsoft Maia, Meta MTIA, and Cerebras wafer-scale racks, all on one stage. When the world's largest AI compute buyers start treating GPUs as "one of the options," the power structure of AI hardware is loosening.


1. OpenAI Jalapeno: Building a Chip in 9 Months

On June 24, 2026, OpenAI, together with Broadcom, unveiled its first self-designed inference ASIC, Jalapeno — the fifth member of the "custom inference chip club."

DimensionJalapeno
PartnerBroadcom + TSMC manufacturing
PositioningInference-specific ASIC
Design cycle9 months end-to-end (Greg Brockman says aided by OpenAI's own models)
Cost target~50% lower token cost vs general-purpose GPU stack
Commercial timingFirst deployments by end-2026; long-term goal 10GW of self-designed chips
Deal scaleUp to $10B strategic partnership with Broadcom (accelerators + networking by 2029)

The talk title "You Can Just Build Things … Chips" is itself a signal: the largest AI compute buyer no longer defaults to GPU as the only path.


2. Google TPU v8: The Biggest Architectural Pivot in a Decade — Train/Infer Split

Google has the longest custom-chip history (2016 to now), and its 8th-gen TPU for the first time splits the product line in two:

ModelCodenamePartnerPositioningKey Specs
TPU 8tSunfishBroadcomTraining9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM, 2× ICI bandwidth
TPU 8iZebrafishMediaTekInference288GB HBM, 384MB on-chip SRAM (3× prior gen), 19.2 Tb/s ICI

On capacity, Morgan Stanley estimates based on supply-chain interviews that Google TPU production in 2026 may exceed 3 million units (a brokerage estimate, not an official target). Google is also the only vendor to achieve large-scale custom-chip deployment and sell compute externally (Gemini runs on TPUs).


3. Meta MTIA: From Recommendation Systems to a GenAI Dual Mission

Meta's custom journey has the clearest starting point — MTIA was originally built for recommendation ranking hardware and is being pulled toward a dual mission by generative AI.

  • MTIA 300 is deployed; 400 / 450 / 500 are planned at roughly one new model every 6 months through 2027;
  • Based on RISC-V, Meta claims up to 25× compute gain;
  • Node evolves with industry cadence: 100 (7nm) → 200 (5nm) → 300 series (3nm + CoWoS);
  • In partnership with Broadcom; another chip codenamed Iris reportedly passed testing in July 2026;
  • Meta plans to start volume production of one of them in September 2026, doubling its overall compute.

4. Microsoft Maia 200/300: Most Advanced Deployment

Microsoft's Maia 200, released January 26, 2026, is the most advanced in deployment among the four:

DimensionMaia 200
ProcessTSMC 3nm, 140B+ transistors
Compute10+ PFLOPS FP4 / 5 PFLOPS FP8
Memory216GB HBM3E, 7 TB/s
Power750W
DeploymentAlready running in Des Moines data center, serving OpenAI GPT-5.2 and Microsoft 365 Copilot

Microsoft claims roughly 3× the performance of Amazon's Trainium on specific benchmarks. The short-term strategy is a dual track of "self-designed Maia + purchased NVIDIA" in parallel — self-designed chips need time from design to mass production, and NVIDIA's mature ecosystem cannot be replaced in the short term.


5. Amazon Trainium 3 and Anthropic's In-House Team

  • Amazon: The Trainium series is already commercial, with 1.4 million units cumulatively deployed (officially disclosed) — a multi-billion-dollar business; its strength is the AWS customer base, letting enterprises choose between NVIDIA GPUs and self-designed chips. Trainium 3 continues this path.
  • Anthropic: In August 2026 announced the formation of an in-house chip team, with no tape-out or mass-production timeline yet; initially positioned as a complement (not a replacement) to existing partnerships with NVIDIA/AMD/AWS/Google Cloud, aiming to tailor-build for the Claude architecture and shed reliance on a single GPU.

6. NVIDIA's Answer: Not a Faster GPU, But Full-Stack

It's easy to simplify the narrative to "four companies build chips, NVIDIA defends GPU." But NVIDIA took 6 slots at Hot Chips: a RISC-V tutorial, the Vera CPU, the Rubin GPU, the BlueField-4 DPU, the Spectrum-X multi-plane network, and an LPU accelerator.

A hyperscaler ASIC replaces only one of those five pillars. If the CPU, NIC, switching fabric, and software all come from the same vendor, what you save by swapping out the accelerator is far less than the accelerator line item on the bill suggests. Rubin's play is a full-stack AI factory platform spanning seven chips and five racks — the competitive answer is "full-stack positioning," not "a faster single chip."


7. Trend Judgment: Inference De-GPU-izes, Training Still GPU-Led

  • Inference side: The CUDA moat visibly shallows. Inference is parallelizable and replaceable at the endpoint; custom ASICs trade away the generality tax (implementing only the operations LLMs actually execute) for lower cost/token. Groq LPU, Cerebras, and various TPU/ASIC players all compete on the same metric.
  • Training side: Foundation models are still trained on GPUs, with no serious challenger in the short term. NVIDIA's three training moats (fastest silicon + NVLink + CUDA) remain firm.
  • Conclusion: Custom chips are not "replacing NVIDIA," but giving buyers a credible external negotiation option in the largest and fastest-growing battlefield — inference. That alone is enough to reshape the economics of AI infrastructure.

References


This article is compiled from August 2026 Hot Chips on-site reports, corporate announcements, and industry analysis. Some capacity and performance figures are brokerage estimates or vendor-disclosed figures; actual results are subject to mass-produced products.

2026 H2 AI Chip Roadmap Major Update: Qualcomm Enters, AMD MI400 Three Models Unveiled, Huawei Three-Generation Roadmap

· 7 min read
AI Hardware Analyst

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.


Key Takeaways

  • Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
  • AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
  • Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
  • Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
  • NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

1. Qualcomm: Mobile Giant Moves Into Datacenter AI

AI 100 → AI 200 → AI 250

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

ModelLaunchAvailabilityKey Features
AI 1002025-102026 H2Rack-scale AI inference, 768GB LPDDR per card
AI 2502025-102027 H1Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed

  1. Low TCO: LPDDR memory is far cheaper than HBM
  2. Energy efficiency: Mobile chip design heritage, excellent power control
  3. Inference-focused: Not chasing training performance, focused on inference scenarios
  4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact

  • Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
  • Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
  • Diversifies choice: Breaks NVIDIA's monopoly in the inference market

2. AMD MI400 Series: Three Models, Precise Positioning

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)

FeatureSpec
PositioningHPC + sovereign AI
FP32/FP64Supported (key differentiator)
Use casesScientific computing, climate simulation, national AI infrastructure
CompetitorNVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)

FeatureSpec
PositioningEnterprise 8-GPU servers
CompatibilityWorks with existing datacenter infrastructure
Use casesEnterprise AI, private cloud, edge inference
AdvantageCheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)

FeatureSpec
PositioningFlagship AI training + inference
Optimized precisionFP4/FP8/BF16
Helios rackCore component
CompetitorNVIDIA Rubin R200

Helios Rack-Scale Solution

AMD also launched the Helios rack-scale AI solution at CES 2026:

  • 18 Zen 6 CPUs (2nm process)
  • 72 MI455X GPUs
  • Direct liquid cooling
  • Shipment expected in 2026 H2

3. Huawei Three-Generation Roadmap: 950 → 960 → 970

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)

ModelLaunchKey Features
950PR2026-Q1PR (inference-optimized), already in mass production
950DT2026-Q4DT (Decode + training), expected to scale up

Technical highlights:

  • Added FP8/MXFP8/MXFP4 support
  • Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)

  • Doubled compute: All specs double versus the 950 series
  • FP8: ~2 PFLOPS expected
  • Process: N+3 (equivalent to 5nm)
  • Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)

  • Third-generation flagship: Only timeline announced, specs TBD
  • Significance: Huawei's first complete generation-spanning roadmap
  • Signal: China's domestic AI chips have entered a "roadmap-driven" phase

4. Intel Jaguar Shores: Timeline Uncertain

Original Plan

  • Launch: 2026
  • Architecture: Xe-HPC + Gaudi fusion
  • Process: 18A (Intel's most advanced)
  • Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments

  • Possible delay: Some sources suggest a slip to 2027
  • Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
  • Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.


5. NVIDIA Rubin Platform: Full Mass Production

Rubin R200 (2026-Q2 full mass production)

FeatureSpec
HBM288GB HBM4
Compute50 PFLOPS FP4
NVLinkNVLink 6 (1800 GB/s)
ProcessTSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)

  • 72 Rubin GPUs
  • 36 Vera CPUs
  • 1.8 EFLOPS FP4
  • Direct liquid cooling

Vera CPU (Debut)

  • Architecture: Custom CPU replacing Grace
  • Positioning: Deep co-design with Rubin GPU
  • Significance: NVIDIA's transformation from a GPU company into a computing platform company

6. Google TPU v8: Training/Inference Officially Split

TPU 8t (training) + TPU 8i (inference)

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

FeatureTPU 8t (training)TPU 8i (inference)
OptimizationHigh compute, high bandwidthLow latency, low cost
InterconnectOptical interconnectEthernet
Launch20272027

Significance

  • Industry trend: Specialization of training/inference chips
  • Followers: Qualcomm AI 200 is also inference-only
  • NVIDIA pressure: Does it need an inference-specific chip?

7. Cerebras WSE-4: Wafer-Scale Engine Evolves

Core Specs

FeatureSpec
Transistors1.4 trillion
Compute125 PFLOPS FP8
Launch2026 H2
ProcessTSMC 5nm

Competitive Advantages

  • Massive model training: A single WSE-4 can train 10T+ parameter models
  • Low-latency inference: Entire model on one chip, no communication overhead
  • Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

8. Market Landscape Analysis

Training Market

RankVendorProductMarket Share (est.)
1NVIDIARubin R20070%
2AMDMI455X15%
3GoogleTPU v8t10%
4HuaweiAscend 9605% (mostly China)

Inference Market (New Battlefield)

RankVendorProductAdvantage
1NVIDIAH200 / Rubin CPXMature ecosystem
2QualcommAI 200Low TCO
3AMDMI440XGood compatibility
4IntelGaudi 4Low price

Trend 1: Rise of Inference-Specific Chips

  • Qualcomm AI 200: Mobile giant enters the market
  • NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
  • Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard

  • NVIDIA NVL72: 72 GPU + 36 CPU
  • AMD Helios: 18 CPU + 72 GPU
  • Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase

  • Huawei three-generation roadmap: 950 → 960 → 970
  • Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
  • Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck

  • SK hynix: HBM4 capacity already booked by NVIDIA
  • Samsung: HBM4E samples delivered to AMD
  • Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

10. Procurement Recommendations

If Procuring in 2026 H2

  1. Training scenarios:

    • First choice: NVIDIA Rubin R200 (best performance)
    • Alternative: AMD MI455X (better price/performance)
    • Domestic: Huawei Ascend 950DT (China-based customers)
  2. Inference scenarios:

    • First choice: NVIDIA H200 (mature ecosystem)
    • Best value: Qualcomm AI 200 (if available)
    • Cost-sensitive: AMD MI440X
  3. HPC scenarios:

    • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027

  • Wait for Rubin Ultra: Performance possibly 2x R200
  • Watch MI500: AMD's next-generation product
  • Evaluate TPU v8: If already on Google Cloud

Conclusion

2026 H2 will be the most fiercely contested half-year in AI chip market history:

  • NVIDIA continues to lead, but its advantage is narrowing
  • AMD precisely positions three models; market share will keep rising
  • Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
  • Huawei has a clear three-generation roadmap; domestic substitution accelerates
  • Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.


References

  • AI Compute Card Future Roadmap - MirrorFrog real-time updates
  • NVIDIA Rubin R200 deep dive (see related articles on this site)
  • AMD MI400 series CES 2026 launch (see related articles on this site)
  • Qualcomm AI 100 launch analysis (coming soon)

Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

Google TPU 8i/8t Officially Launched: Training and Inference Split for the First Time, 2nm Process Powers the Agentic Era

· 7 min read
Industry Research Team

On April 22, 2026, at Google Cloud Next '26 in Las Vegas, Google officially launched its 8th-generation Tensor Processing Unit (TPU). For the first time in Google's history, it split AI training and inference onto two independent chips:

  • TPU 8t: designed for model training
  • TPU 8i: focused on high-concurrency inference

This launch introduces no new physical concept, but focuses on solving the core pain points of AI data centers: ten-thousand-card cluster scaling efficiency, Agentic AI workload optimization, and performance per watt.

TPU 8i (inference-specific): eliminating the "waiting room effect"

TPU 8i is the first inference-specific chip co-designed by Google and MediaTek, aimed at eliminating the "waiting room effect" — where user requests are intentionally queued or delayed to maximize hardware utilization.

TPU 8i core specs (estimated)

ParameterTPU 8iTPU v7 Ironwood
PositioningInference-specificMostly inference
ProcessTSMC 2nm
Die designDual compute die (est.)
Memory8× HBM3e 12-layer (~192GB est.)8× HBM3 (192GB)
Memory bandwidth~7 TB/s (est.)7,380 GB/s
FP8 compute~4,614 TFLOPS (est.)4,614 TFLOPS
TDP (per chip)1,300 W1,000 W
InterconnectICI 3D TorusICI 3D Torus
Integrated CPUArm Axion (64 cores)None
CoolingAir or liquid4th-gen liquid
Announced2026-04-222025-08-25
Mass productionEnd of 20272026

Key features:

  • High-concurrency inference optimization: built for Agentic AI, supports inference chains of thousands of steps
  • Arm Axion CPU integration: 64-core Neoverse V2, host CPU + data preprocessing synergy
  • Low latency: eliminates the "waiting room effect", extremely low TTFT (time to first token)
  • 117% better performance per watt: vs Ironwood (at equal price)

TPU 8t (training-specific): the "engine" of Gemini 3/4

TPU 8t is designed for training Google's frontier models like Gemini 3 / Gemini 4, continuing Google's long-term partnership with Broadcom.

TPU 8t core specs

ParameterTPU 8tTPU v7 IronwoodImprovement
PositioningTraining-specificMostly inferenceForm-factor split
ProcessTSMC 2nmNew gen
Die designDual compute dieArchitecture upgrade
MemoryHBM3e 12-layer (~256GB per chip est.)8× HBM3 (192GB)Upgrade
Memory bandwidth~7 TB/s (per chip est.)7,380 GB/sFlat
Pod chip count9,600 chips9,216+4%
Pod total HBM2 PBFar exceeds
Pod FP4 compute121 EFLOPS~42 EFLOPS (est.)~3×
Integrated CPUArm Axion (64 cores)NoneNew
TDP (per chip)1,300 W1,000 W+30%
Mass productionEnd of 20272026

Key features:

  • Native MoE training support: Expert-Parallel optimization (DeepSeek / Mixtral style)
  • Long-context training: 1M+ token context training optimization
  • RLHF / post-training: native Online RL (DPO/PPO/GRPO) optimization
  • Arm Axion CPU synergy: data preprocessing / weight init offloaded to CPU
  • SparseCore acceleration: MoE routing and recommendation systems

Strategic significance of the 8th-generation TPU

1. Training and inference split for the first time

Previously, Google's TPU design philosophy was "one architecture for both training and inference" (e.g., TPU v5p, v6e). But the arrival of the Agentic AI era changed that:

  • Training workloads: large-scale matrix multiply, long-sequence backpropagation, sparse MoE
  • Inference workloads: high concurrency, low latency, KV Cache-intensive, dynamic batching

These two workloads impose very different demands on chip architecture. After the split:

  • TPU 8t can focus on optimizing compute density and memory capacity
  • TPU 8i can focus on optimizing inference throughput and performance per watt

2. Dual-track partnership with Broadcom and MediaTek

  • Broadcom: continues designing TPU 8t (training), extending the long-term partnership since TPU v1
  • MediaTek: first-time collaboration designing TPU 8i (inference), bringing mobile-chip low-power design expertise

This "dual-track" strategy lets Google:

  • Pursue peak performance on training chips (combined with Broadcom's high-end ASIC experience)
  • Pursue peak energy efficiency on inference chips (combined with MediaTek's mobile-chip experience)

3. Versus NVIDIA Vera Rubin

ComparisonGoogle TPU 8t + 8iNVIDIA Vera Rubin
StrategyTraining/inference splitUnified architecture (GPU+CPU)
ProcessTSMC 2nmTSMC 3nm (est.)
EcosystemGoogle Cloud onlyGlobally available
SoftwareJAX / PyTorch-XLACUDA / PyTorch
Mass productionEnd of 2027Fall 2026
StrengthDeep Gemini integrationMost mature ecosystem

Deep technical analysis

TSMC 2nm: why 2nm?

Google is the first vendor to adopt TSMC 2nm on an AI accelerator (NVIDIA Rubin uses 3nm). 2nm (N2) vs 3nm (N3E):

  • Transistor density: ~15-20% higher
  • Power reduction: ~25-30% (at equal performance)
  • Performance gain: ~10-15% (at equal power)

For TPU 8t/8i, which already hit 1,300W, 2nm is mandatory — otherwise 4nm/3nm couldn't integrate dual compute dies and 8× HBM3e within reasonable power.

Arm Axion CPU: Google's in-house CPU enters the TPU node for the first time

Previously, TPU nodes used Intel Xeon or AMD EPYC as host CPUs. TPU 8t/8i integrate Google's in-house Arm Axion CPU (64-core Neoverse V2) for the first time:

Significance:

  1. Data preprocessing offload: tokenization, data augmentation can run entirely on Axion, freeing TPU compute
  2. Weight initialization: large-model training weight init on CPU, accelerating training startup
  3. Inference scheduling: Axion handles request scheduling and load balancing for multi-model inference

This marks the TPU node's evolution toward a "SuperNode": no longer a pure accelerator, but a TPU + Axion CPU co-design system, comparable to NVIDIA's Vera CPU.

4th-gen liquid cooling: the 1,300W thermal challenge

TPU 8t/8i TDP reaches 1,300W (30% over Ironwood's 1,000W), posing a huge data-center cooling challenge.

Google adopts a 4th-gen liquid cooling solution:

  • Cold-plate liquid cooling: directly cools GPU die and HBM
  • Immersion cooling: optional (ultra-high-density deployment)
  • Smart thermal control: dynamically adjusts pump speed and fan RPM by workload

Production timeline and use cases

TimeEvent
2026-04-22Cloud Next '26 official announcement
H2 2026Internal testing (Google DeepMind first)
End of 2027Mass production, Google Cloud availability
2028Next-gen TPU (possibly TPU 9)

Target use cases:

  • Frontier model training (Gemini 3/4, external customers)
  • MoE large-model inference (high concurrency, low latency)
  • Multimodal AI (ViT + LLM simultaneous inference)
  • Agentic AI (Agentic AI workloads)

Competitive comparison

VendorProductProcessTDPMass production
GoogleTPU 8i (inference)TSMC 2nm1,300WEnd of 2027
GoogleTPU 8t (training)TSMC 2nm1,300WEnd of 2027
NVIDIARubin GPUTSMC 3nm (est.)~1,000WFall 2026
NVIDIAVera CPUTSMC 3nm (est.)~500WFall 2026
AMDMI455X (MI400)TSMC 3nm (est.)~700W2026
HuaweiAscend 950PR~500WQ1 2026

Industry impact

  1. AI chips enter the 2nm era: Google leads with TSMC 2nm; NVIDIA and AMD will follow
  2. Training/inference split becomes a new trend: other vendors (NVIDIA, AMD) may follow suit
  3. In-house CPUs become standard: Google (Axion), NVIDIA (Vera), Huawei (Kunpeng) all do CPU+accelerator co-design
  4. Liquid cooling becomes inevitable: 1,300W TDP means air cooling can no longer suffice

References


This article is compiled from Google's official announcements and public sources; some specs are estimates, subject to final official release.