6 posts tagged with "HBM4"

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

9 月第一周，存储行业传来三组关键信号：SK 海力士面向英伟达 Vera Rubin 平台量产交付全球首款 12 层 HBM4；三星 Q2 HBM 份额飙升至 33%、直逼王座；美光宣布年底 HBM 月产能翻倍至约 10 万片晶圆。 HBM4 的竞争，已经从"谁能造出来"变成"谁能最快量产爬坡、谁绑定的客户最深"。

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1. 三巨头战报：领跑者、追赶者与搅局者​

维度	SK 海力士	三星电子	美光
HBM4 关键节点	2026 年中向 Vera Rubin 量产交付 12 层 HBM4（全球首款完整质量认证）	2026 年 2 月全球首家大规模量产出货	2026 Q2 量产 12 层 HBM4，批量出货
DRAM 核心裸片	1b（第五代 10nm 级）	1c（第六代）	—
Base Die 代工	台积电 12nm	自家 4nm	拟转台积电（1γ 工艺代）
2026 HBM4 份额预测	~54%	~28%	~18%
Q2 HBM 营收份额	50%（环比 -14pct）	33%（环比 +12pct）	18%
HBM 产能	~15–20 万片/月	~15–20 万片/月	年底冲刺 10 万片/月（现为 4–5 万）

三个关键读数：

• 三星的反扑是真的：从去年 Q2 份额低至 15%（落后美光 6 个百分点）到今年 Q2 的 33%，三星用一年时间把与 SK 海力士的差距缩小到 17 个百分点。三星预计 HBM4 将占其下半年 HBM 收入的 60% 以上，且现有 HBM4 产能已被客户预订售罄，2026 年 HBM 总产能计划提升约 50%；
• 美光的追赶也是真的：CEO 梅赫罗特拉透露 12 层 HBM4 爬坡速度约为 HBM3E 的两倍、累计收入已超 10 亿美元；年底若如期达成 10 万片月产能，与两强的差距将缩小一半；
• SK 海力士的护城河依然深：与英伟达签署多年期 HBM/DRAM 供应协议、率先完成 2027 年 HBM4 价格谈判，在英伟达 HBM4 采购中占比约 60%（乐观情形 70%）。

2. 变局核心：封装比 DRAM 制程更值钱​

HBM4 与 HBM3E 时代最大的不同，是胜负手从存储颗粒转向了封装与 Base Die：

• I/O 通道数从 1024 条翻倍至 2048 条，单颗 12 层封装吞吐超 2TB/s，能效较前代提升逾 40%；
• Base Die 首次引入晶圆代工厂先进逻辑工艺——SK 海力士用台积电 12nm，三星用自家 4nm，美光计划在 1γ（首次导入 EUV）世代转由台积电代工；
• 存储原厂与代工厂的协作深度，第一次成为决定出货速度的关键变量——这正是 Hot Chips 2026 上"三星 HBM Base Die 逻辑工艺化"议题的产业注脚。

SEMI 数据显示，2026 年全球 HBM 市场规模预计增长 58% 至 546 亿美元，约占 DRAM 市场四成。行业预计 HBM4 销售占比将在 2026 年 Q4 正式超越 HBM3E，成为市场主流。

3. 客户端信号：Rubin 加码，Rubin CPX 重生​

需求端同样在 9 月出现重要变化：

• Vera Rubin 全面量产（详见本站专文）：每颗 Rubin GPU 搭载 288GB HBM4、带宽 22TB/s，NVL72 整柜 75TB 快速内存——HBM4 供给直接决定 Rubin 出货上限，这也是英伟达把"先进晶圆与 HBM 供应"列为当前第一约束的原因；
• Rubin CPX 项目重启：据 CFM 闪存市场 9 月 2 日简讯，英伟达重启此前搁置的 Rubin CPX 机柜项目，内存规格由 128GB GDDR7 改为 168GB HBM4，机架改为独立 MGX ETL 设计，客户可选 64/128/192/256 颗 GPU 配置——推理专用卡也全面转向 HBM4，进一步放大了 HBM4 需求；
• 供给协议长期化：英伟达已与 SK 海力士、美光签署多年期 HBM 及 DRAM 供应协议，锁供给、锁价格、锁产能成为巨头标配动作。

4. 下半场：HBM4E 已经鸣枪​

下一代产品的竞争在 2026 年同步开启：

• SK 海力士：HBM4E 送样提前至 2026 年年中（原计划下半年），COMPUTEX 2026 已展出 12 层样品，单引脚速率最高 16Gbps、单堆栈带宽约 4TB/s，计划 2027 年量产；
• 三星：2026 年 Q2 起向头部客户交付业界首批 HBM4E 样品（48GB），目标 2027 年拿下 HBM4E 市场 50% 以上份额；
• 美光：HBM4E 预计 2027 年量产，首批样品采用 1γ 制程 DRAM。

5. 对采购方与投资观察者的启示​

• 供应商组合成为第一优先级采购变量：同样买 Rubin 平台，采用哪家 HBM 供应商的整机，交付周期可能相差数月；
• 国产链条的机会窗口：HBM 供不应求叠加出口管制，长鑫等国产存储玩家的 HBM 进展值得持续跟踪——国产 AI 芯片（昇腾 950 系列等）对 HBM 的需求同样在放量；
• 跟踪三个领先指标：头部云厂商 Rubin 机架采购量、HBM 设备供应商订单（美光已加大 PO）、HBM4E 送样→量产的时间差。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin CPX 规格页
• NVIDIA Rubin Ultra 规格页

参考资料​

• Electronic Times：US Micron to Double HBM Capacity, Closing Gap with Samsung and SK（2026-09-04）
• Korea Herald / News18：Samsung narrows SK hynix HBM lead as HBM4 shipments accelerate（2026-09-04）
• CFM 闪存市场：HBM4 量产爬坡竞速与 Rubin CPX 重启简讯（2026-09-02/04）
• 快科技：美光吹响反击号角！HBM4 产能翻倍直追三星海力士（2026-09-04）

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本文基于 2026 年 9 月初 Counterpoint Research、CFM 闪存市场及韩媒报道整理。份额与产能数据均为研究机构/供应链预估口径，实际以各原厂财报为准。

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

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1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

Timeline	Samsung HBM4 Yield	Notes
Feb 2026 (mass production start)	Under 60%	Line ramp-up period
Early Aug 2026	~80%	Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

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2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor	2026 Rubin HBM4 Allocation (est.)	Notes
SK Hynix	60%–70%	Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung	25%–30%	Rapid share gains after yield leap
Micron	Remainder	Limited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

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3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

• Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
• HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
• Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

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4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

Spec	HBM4 (12-Hi / 16-Hi)	HBM4E
Per-stack capacity	36 GB / 48 GB	—
Pin rate	11.7–13.0 Gbps	16 Gbps
Per-stack bandwidth	up to 3.3 TB/s	up to 3.6 TB/s
Bus width	2048-bit	—
Energy efficiency	+40% vs HBM3E	—
Thermal resistance / cooling	+10% improvement / +30%	—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

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5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

• 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
• The industry already anticipates significant price increases;
• For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

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6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

Related Links​

• NVIDIA Rubin Spec Page
• AMD MI455X Spec Page
• Hot Chips 2026 Full Recap

References​

• Samsung's HBM4 Yield Hits 80% as HBM Race Heats Up - TrendForce
• Samsung HBM4 Yield Hits 80%, Boosting AI Memory Supply - PC Central
• Samsung Weighs Shipping Legacy Memory Backend to Vietnam to Unlock HBM Capacity - TechTimes
• 芯闻|六个月良率跃迁：三星HBM4突破80%黄金门槛 - Toutiao

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This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

AMD has confirmed its flagship AI event Advancing AI 2026 will be held July 22-23, 2026 at the Moscone Center in San Francisco, with the keynote on July 23 hosted by Chair and CEO Lisa Su. The event will complete the Instinct MI400 series availability timeline, pricing, and independent benchmark data.

1. Instinct MI400 family: three CDNA 5 accelerators​

AMD fully revealed the MI400 matrix at CES 2026; all three accelerators use CDNA 5 architecture, TSMC 2nm process, differentiated by precision and scenario:

Model	Positioning	Key specs
MI455X (flagship)	Large-scale train/inference (rack-scale)	320B transistors, 12 chiplets, 432 GB HBM4 (12×36GB), 19.6 TB/s, FP4 40 PFLOPS / FP8 20 PFLOPS
MI440X (enterprise)	Local enterprise AI (8-card node)	Low-precision AI (FP4/FP8/BF16), direct MI300/MI350 replacement, compatible with existing power/cooling
MI430X (HPC/sovereign AI)	High-precision scientific computing + AI	Full FP32/FP64, already deployed at Oak Ridge Discovery and France's first exascale Alice Recoque

MI455X and MI440X target low-precision AI (FP4/FP8/BF16); MI430X fills traditional HPC high-precision needs — improving energy efficiency and cost-performance by "trimming execution units by precision." All three support UALink (among the first accelerators compatible with the standard) and Infinity Fabric die-to-die interconnect; rack scaling uses Ultra Ethernet.

Lisa Su confirmed on the Q1 2026 earnings call: MI455X samples have been sent to core customers, with demand "exceeding the company's internal expectations for 2027."

2. Helios rack: 3 exaFLOPS per cabinet​

AMD enters the hyperscale market with the Helios rack-scale platform:

Metric	Helios rack
Accelerators	72 × MI455X
Aggregate HBM4	31 TB
Total memory bandwidth	1.4 PB/s
Per-cabinet compute	Up to 3 AI exaFLOPS (Q3 delivery target)
Target customers	Hyperscale train/inference clusters

Helios uses AMD's in-house Zen 6 EPYC Venice CPU (18 per rack) + Pensando Vulcano 800G NIC, integrated via the open ROCm software stack; AMD also plans a double-width 128-card Helios variant, pushing per-cabinet compute to the 3 AI exaFLOPS ceiling. Further out, the MI500 series (CDNA 6, 2nm, HBM4E) is planned for 2027, with official claims of up to 1000× AI performance vs MI300X.

3. 12GW deal: OpenAI + Meta dual endorsement​

AMD holds two historic-scale compute agreements totaling about 12 GW, with lifetime potential revenue possibly reaching $100B:

Customer	Scale	First deployment	Structure
OpenAI	6 GW (multi-gen products)	First 1 GW, H2 2026 on MI450	"compute-for-upside": up to 160M warrants, vesting by milestone and stock-price targets
Meta	6 GW	Custom MI450 chips, from H2 2026	Deployed in next-gen data centers

Financial expectations​

Metric	2026 forecast
MI400 series revenue	~$7.2B (about 25% of data-center sales)
Data-center GPU revenue	~$15B (up +114% YoY)
Total data-center revenue	Possibly $28.7B (up +73% YoY)

⚠️ Execution risk: AMD has flagged that MI450's Q3 mass production will weigh on gross margin (new products below company average); advanced process and advanced packaging (TSMC CoWoS) capacity remain the main constraint.

Industry interpretation​

1. CUDA moat being pried open: when companies building the world's largest training clusters — Meta, OpenAI — bet on AMD silicon, AMD's long-standing 5-7% GPU share ceiling is being broken.
2. Memory advantage as differentiation: 432 GB HBM4 / 19.6 TB/s vs NVIDIA Rubin's 288 GB offers capacity advantage, critical for large-model inference (KV Cache-constrained scenarios).
3. Tight benchmarking pace: MI450 and NVIDIA Vera Rubin both ramp in H2 2026, with the two giants competing head-on over HBM4 supply and CoWoS capacity.

Related links​

• AMD Instinct MI455X specs
• AMD Instinct MI400 specs
• AMD Instinct MI350 specs

References​

• AMD sets July date to detail its Instinct MI400 AI accelerators - IT Magazine
• Lisa Su: AMD has sent MI450 GPU samples to core customers - AGI.Space
• AMD and OpenAI announce strategic partnership to deploy 6GW AMD GPU - AMD press release
• AMD's 12-Gigawatt AI Contract Haul - StocksToday

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This article was written on the eve of Advancing AI 2026 (July 22-23, opening tomorrow); the keynote is July 23 hosted by Lisa Su, where MI400's final availability, pricing, and independent benchmarks will be revealed — we will update in sync.

July 2026, NVIDIA's next-gen AI compute platform Vera Rubin officially began its first shipments, succeeding the Blackwell architecture, with large-scale mass production planned for H2 2026. First customers include Microsoft, Google, Amazon, Meta, Oracle, and other large cloud providers.

1. World's First VR200 NVL72 Delivered (Milestone)​

CoreWeave jointly with Dell announced that the world's first NVIDIA Vera Rubin VR200 NVL72 cabinet has been officially delivered and passed the L11 full-cabinet hardware diagnostics on the first try. This marks Rubin's move from roadmap to physical product, with no major bottlenecks in core supply-chain links (HBM4, advanced packaging, liquid cooling, ultra-high-power power supply).

VR200 NVL72 Core Configuration​

Metric	Vera Rubin VR200 NVL72
Cabinet codename	Oberon
GPU	72 Rubin GPUs
CPU	36 Vera CPUs
Per-GPU memory	288 GB HBM4
Per-CPU memory	1.5 TB LPDDR5X
Total cabinet HBM4	20.7 TB (20,736 GB)
Total cabinet LPDDR5X	54 TB
Interconnect	NVLink 6 full mesh
Inference performance	~3.6 exaFLOPS class
Cooling	Liquid cooling
Generational improvement	~3.5× per-GPU compute, ~2.8× memory bandwidth (vs Blackwell)

Vera CPU integrates 88 custom Olympus ARM cores, with 1.8 TB/s interconnect to the GPU, usable as a GPU memory expansion pool. NVIDIA completed its first Vera CPU deliveries to Anthropic, OpenAI, xAI, and Oracle Cloud in May.

2. Samsung HBM4 Mass Production: Key Bottleneck Eases​

July 8, 2026, Samsung Electronics officially started HBM4 mass production for the Vera Rubin platform, with reported HBM4 mass-production yield reaching 70% (above the initial 60-65% expectation). Confirmation of this key supply-chain link clears obstacles for Rubin's large-scale deployment.

HBM Supply Landscape (2026 Q1)	Share
SK hynix	45%
Samsung	40%
Micron	15%

HBM4 uses 8-layer stacking (12-layer design planned for 2028), priced at about 2.8× HBM3e. TrendForce predicts HBM supply will grow 65% annually, with HBM4 reaching 35% of total output by 2027 Q4.

3. Rubin Ultra Sky-High Price: HBM Cost Dominates​

Per BofA Global Research estimates, the Rubin generation will push single-server cost to a new high:

Cost Item	Rubin VR200 (Oberon)	Comparison
Cabinet HBM4 usage	20,736 GB	—
HBM4 unit price	~$18.40 / GB	Blackwell (HBM3e) ~$11.26 / GB
HBM4 cost alone	~$382K	Excluding LPDDR5X
Rubin Ultra cabinet estimated price	~$21M	ITHome / BofA estimate

4. Rubin Ultra Design Change: Original 4-die Cancelled (per SemiAnalysis)​

Semiconductor research firm SemiAnalysis (2026-06-30) disclosed that the original 4-die Rubin Ultra GPU unveiled at GTC 2026 has been cancelled; the version actually shipping in 2027 is roughly halved in scale and performance:

• Reason for cancellation: The original integrated 4 compute dies + 16 HBM4E in a single CoWoS-L package; the substrate warped under the 4-die config, causing compute-die-to-substrate contact failure and yield collapse; the alternative CoPoS won't reach mass production until after late 2028, missing the 2027 node.
• New approach: Changed to dual-die (same construction as standard Rubin) + HBM4E, ~384 GB HBM4E per GPU (higher than standard Rubin's 288 GB), but total compute and bandwidth only half the original; to approach the original's aggregate compute, NVIDIA plans to assemble "2+2" board-level configs within the Kyber rack to reach four-die equivalent scale.
• Kyber rack delay: The companion Kyber NVL144 rack is delayed 12+ months to 2028 due to midplane PCB manufacturing difficulties; the 800V DC power scheme is likewise delayed to 2028.

⚠️ Note: NVIDIA has not commented officially on the above design change; some on X argue "the chip count hasn't changed, it's old news reheated." This section is compiled from SemiAnalysis public reports, subject to final NVIDIA disclosure. We have marked "specs pending official confirmation" on the Rubin Ultra preview card.

Industry Interpretation​

1. "Never doubt" moment realized: Rubin's first delivery passed L11 on the first try, dispelling market doubts about "Rubin delay," locking in H2 2026 AI compute supply certainty ahead of time.
2. Designed for Agentic AI: Rubin targets agentic workflows and ultra-long-context inference, further lowering the training/inference cost curve for trillion-parameter models.
3. HBM is the full-chain winner: 20.7 TB HBM4 per cabinet is enormous usage; SK hynix, Samsung, Micron, advanced packaging (CoWoS-L), liquid cooling, and power retrofitting all benefit across the chain, while also becoming the biggest cost and capacity constraint.

Related Links​

• NVIDIA Rubin R200 spec page
• NVIDIA Vera CPU spec page
• NVIDIA Rubin CPX spec page

References​

• Samsung Starts Mass Production for Nvidia's Vera Rubin AI Platform (2026-07-08)
• Rubin cabinet first delivery: CoreWeave and Dell deliver world's first VR200 NVL72
• Nvidia Rubin Ultra cabinet estimated at $21M - ITHome (2026-07-09)
• NVIDIA Vera Rubin scheduled for July 2026 shipment - VendorDeep

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This article continuously tracks Vera Rubin mass-production ramp and HBM4 supply-chain dynamics.

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights​

• MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
• MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
• Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
• Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
• Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
• Architecture upgrade: from CDNA 4 to CDNA 5
• Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs​

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

Model	Positioning	Memory	FP4 compute	FP8 compute	TDP (est.)
MI455X	Flagship training+inference	432GB HBM4	40 PFLOPS	20 PFLOPS	~1,000W
MI450	Cost-performance training	288GB HBM4	28 PFLOPS	14 PFLOPS	~800W
MI440X	Enterprise inference	216GB HBM4	25 PFLOPS	12.5 PFLOPS	~600W
MI430X	HPC / scientific computing	192GB HBM4	20 PFLOPS	10 PFLOPS	~500W
MI400X	General / edge inference	128GB HBM4	12 PFLOPS	6 PFLOPS	~400W

Key upgrades (vs MI350 series):

• Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
• Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
• Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +2×)
• Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
• Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X​

Metric	MI355X (2025)	MI455X (2026)	Improvement
FP4 compute	20 PFLOPS	40 PFLOPS	2×
FP8 compute	10 PFLOPS	20 PFLOPS	2×
Memory capacity	288GB HBM3e	432GB HBM4	1.5×
Memory bandwidth	8 TB/s	19.6 TB/s	2.45×
Process	TSMC 3nm	2nm + 3nm hybrid	New gen
Architecture	CDNA 4	CDNA 5	New gen
TDP	800-1000W	~1,000W	Flat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail​

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades​

1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
4. Native sparsity support: MoE Expert-Parallel optimization
5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin​

Metric	AMD MI455X	NVIDIA B200	NVIDIA Rubin R200 (2026 Q4)
FP4 compute	40 PFLOPS	20 PFLOPS (45 sparse)	~40 PFLOPS (est.)
FP8 compute	20 PFLOPS	10 PFLOPS (22.5 sparse)	~20 PFLOPS (est.)
Memory	432GB HBM4	192GB HBM3e	288GB HBM4
Memory bandwidth	19.6 TB/s	8 TB/s	13 TB/s
TDP	~1,000W	700-1000W	~1,000W
Process	2nm + 3nm hybrid	TSMC 4np	TSMC 3nm
Mass production	2026 Q4	2024 Q4	2026 Q4
Software ecosystem	ROCm	CUDA	CUDA
Strength	Memory capacity, open ecosystem	Most mature ecosystem	Next-gen architecture
Weakness	Software ecosystem gap	Smaller memory	Not yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline​

Time	Event
June 12, 2025	MI400 series specs first announced at Advancing AI
January 5, 2026	MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3	MI450 sampling begins
2026 Q4	MI455X mass production
2026 Q4	MI440X (enterprise inference) launched
2027 Q1	MI430X/MI400X (HPC/edge inference) launched
2027	MI500 series (next gen)

AMD AI chip roadmap (2025-2027)​

Time	Product	Process	Notes
Q4 2024	MI325X	TSMC 5nm	HBM3e upgraded
Q3 2025	MI355X (MI350 series)	TSMC 3nm	CDNA 4, 288GB HBM3e
Q4 2026	MI455X (MI400 series)	2nm + 3nm hybrid	CDNA 5, 432GB HBM4
Q1 2027	MI500 series	TSMC 2nm (est.)	Next gen, further gains

Software ecosystem: ROCm's progress and challenges​

✅ Progress​

• PyTorch 2.5+: native MI300X/MI455X support
• Hugging Face Transformers: official AMD GPU support
• vLLM 0.8+: MI300X inference support (experimental)
• JAX: AMD adapting (vs Google TPU)

⚠️ Challenges​

• Framework optimization: PyTorch on AMD GPUs still below NVIDIA
• Operator coverage: some niche operators need hand-written HIP
• Multi-card communication: RCCL (vs NCCL) still lags
• Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison​

Vendor	Product	FP4 compute	Memory	Mass production	Strength	Weakness
AMD	MI455X	40 PFLOPS	432GB HBM4	2026 Q4	Largest memory, open ecosystem	Software gap
NVIDIA	B200	20 PFLOPS	192GB HBM3e	2024 Q4	Most mature ecosystem	Smaller memory
NVIDIA	Rubin R200	~40 PFLOPS	288GB HBM4	2026 Q4	Next-gen architecture, CUDA	Expensive
Huawei	Ascend 910C	~1.6 PFLOPS	64GB HBM	2026 Q2	China-localized	Export-controlled
Google	TPU 8t	~9.2 PFLOPS	~256GB HBM3e	Late 2027	Gemini-integrated	Google Cloud only

Industry impact​

1. Impact on NVIDIA​

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

• NVIDIA has the CUDA ecosystem moat
• NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
• AMD only sells cards/nodes, NVIDIA sells AI factories
• MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips​

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

• Catch up to 5nm + HBM3e by 2026-2027
• Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers​

MI455X gives cloud providers a second option beyond NVIDIA:

• Microsoft Azure: already deployed MI355X, may follow with MI455X
• Google Cloud: in-house TPU, won't use AMD
• Amazon AWS: in-house Trainium/Inferentia, won't use AMD
• Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

Related chips​

• AMD MI455X - the new launch
• AMD MI300X - previous flagship
• AMD MI325X - HBM3e upgraded
• NVIDIA B200 - direct competitor
• NVIDIA Rubin R200 - same-generation competitor

References​

• MI455X chip - Baidu Baike - official specs
• AMD drops its most powerful two-gen AI chips! World's first 432GB HBM4 - Zhihu - on-site report
• Taking on NVIDIA: AMD launches MI440X for enterprise AI data centers - Tencent News
• AMD MI400 packs 432GB HBM4: specs crush NVIDIA on paper - CocoLoop
• AMD CES 2026 keynote replay

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This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).