35 posts tagged with "Industry Review"

据 The Gist/The Index Today 10月10日汇总，OpenAI 的商业化图景正以两条相互撕扯的曲线展开：一边是年化营收朝年底约700亿美元的方向快速推进，另一边是 Q2 运营亏损扩大至123亿美元。与此同时，这家公司在企业服务、消费产品与广告变现三条战线上同时铺货，并用数千亿美元级的算力协议锁定未来。本文为您梳理全景。

华为昇腾与寒武纪之外，一批二线国产 AI 芯片厂商正在 2026 年集体进入收获期：上市潮、大厂订单与超节点产品同时落地，国产算力的第二梯队正在成形。

资本市场：从独角兽到上市公司的批量切换​

2026 年是国产 AI 芯片的上市大年。燧原科技的科创板 IPO 已过会并获注册批复，拟募资 60 亿元，公司自研迭代了四代架构、五款云端 AI 芯片；壁仞科技于 2026 年 1 月 2 日在港交所挂牌，开盘大涨 82%，市值一度突破千亿港元，成为港股 GPU 第一股；天数智芯也在 2026 年 1 月登陆港交所。据业界统计，摩尔线程、沐曦等厂商同样在冲刺科创板，"国产 GPU 四小龙"有望在资本市场聚齐。

产品与订单：超节点成为竞争主线​

2026 世界人工智能大会清晰地展示了行业竞争重心的迁移：从单芯片算力比拼转向芯片、高速互联与整机集群的系统级较量。壁仞科技推出基于芯粒架构 BR2xx 芯片的光互连千卡超节点，最多 1024 张 GPU 可共享同一内存空间；燧原科技联合中兴通讯发布的云燧 ESL64-O 超节点采用正交无背板设计，实现零线缆以大幅降低互联成本，其与腾讯云合作的"燎原"智算集群 3.0 已完成数千卡至万卡级部署。

订单侧的突破更具标志性意义。据多家媒体援引消息报道，字节跳动正与天数智芯洽谈采购至少 5 万颗智铠系列云端推理 GPU，若落地将成为继华为、寒武纪之后字节跳动的第三大国产 GPU 供应商；业界普遍认为，国产推理芯片定价约为英伟达同级产品的六到七成，成本优势叠加安全可靠测评的政策导向，正在推动互联网大厂从试点采购转向规模导入。登临科技等专注推理加速的厂商，也在互联网与行业客户中持续推进规模化商用。

生态与隐忧：窗口期不会永远敞开​

软件生态的比拼同样白热化。壁仞科技已对智谱 GLM、DeepSeek、通义千问等 20 余款头部大模型完成当日同步适配，其中 DeepSeek 全系列适配据称仅用数小时；2026 年 5 月，首批 9 款国产芯片获评国家最高安全可靠等级，壁仞、天数智芯等均榜上有名，信创需求的井喷进一步打开了市场空间。

但隐忧同样明确：先进制程产能受限于代工排期，交付能力决定谁能兑现政策红利；英伟达下一代架构随时可能随出口政策变化重返中国市场，国产芯片的时间差优势存在收窄风险。二线厂商能否从"能跑"走向"好用、稳定、规模供货"，仍是决定最终座次的关键。

小结​

2026 年的国产 AI 芯片第二梯队，第一次同时拥有了资本弹药、大厂订单与系统级产品能力。燧原、壁仞、天数智芯的上市潮解决了资金可持续性，超节点与大模型适配解决了生态可用性，剩下的问题——产能与长期竞争力——将在未来两年给出答案。

服务器 CPU 市场正在经历一次角色重定义：AMD 用 2nm 制程和 256 核密度继续扩大领先，Intel 被迫靠涨价在需求中求生，而 NVIDIA 自研 Vera CPU 则带着 AI 专用设计入场。AI 服务器里 CPU 不再是主角，但恰恰因此，它的选型逻辑被彻底改写。

AMD Venice：2nm 量产 + 256 核密度登顶​

AMD 第六代 EPYC "Venice"（Zen 6 架构，最高 256 核）已经在台积电 2nm 产线启动量产，这是行业首批进入 2nm 量产的处理器产品之一。更值得关注的是，量产正在从台积电延伸至 AMD 的亚利桑那工厂——先进制程的美国本土化，对政府采购和主权 AI 项目是重要的加分项。

Venice 还有两层战略价值：其一，它是 Helios 机架（72 颗 MI455X）的配套 CPU，AMD 的 GPU 机架方案因此获得了"自家 CPU+自家 GPU"的垂直整合能力；其二，下一代 "Verano" 已经为 AI 工作负载预留设计，说明 AMD 在产品定义阶段就开始为 AI 节点做优化，而不是拿通用服务器芯片顺手兼容。

Intel：年内三度涨价，份额仍在流失​

Intel 的处境则截然不同。10 月 5 日起，Intel 对 CPU 提价 10%——这是年内第三次涨价，驱动因素是 AI 需求带动的产能紧张。但涨价并没有止住份额流失：多家分析师在报告中持续给出卖出的建议口径，认为 Intel 服务器 CPU 的市场份额下滑尚未见底。

值得注意的悖论是：Intel 涨价的底气部分恰恰来自 AI——AI 服务器爆发也拉动了配套 x86 CPU 的需求，产能紧张让 Intel 敢于连续提价。但"涨价求生"的另一面是，客户在 AI 服务器 CPU 选型上的议价空间被压缩，这反而给了 AMD 和 NVIDIA 更多切入机会。

Vera 入场：AI 节点上的 CPU 重新定义​

NVIDIA 自研的 Vera CPU 是第三个变量。Daytona 基准测试给出了一个惊人的对比：Vera 跑千沙盒仅需 10.8 秒，而 AMD 旗舰 EPYC 9755 需要 88.4 秒——约 8 倍的差距。

Vera 的设计思路与通用服务器 CPU 完全不同：SCF 互联加 1.5TB LPDDR5X 的组合，是专为 AI 节点上"数据搬运 + 调度"的角色优化的。在 Grace/Vera 与 GPU 紧耦合的架构里，CPU 的传统性能指标（如 SPEC 系列）重要性下降，而内存带宽、与加速器的耦合效率成为新的评价维度。

分析：AI 服务器中 CPU 角色的重定义​

AI 服务器里，CPU 不再是算力的主角，而是被压缩到三个角色：主机侧调度（内核、虚拟化、作业分发）、数据搬运（存储/网络与 GPU 之间的通路）、以及配套生态（x86 软件兼容性）。这带来了三强格局下的不同打法：

• AMD 走密度路线：用 256 核 + 2nm 的硬件优势，同时服务传统虚拟化和 AI 机架主机侧，Venice 与 Helios 的绑定让"买 AMD GPU 就配 AMD CPU"成为默认选项；
• Intel 涨价求生：利用产能紧张和 x86 生态惯性提价保收入，份额换取现金流，等待下一代产品翻盘；
• NVIDIA 自研入场：Vera 不参与通用服务器竞争，只在 AI 节点上用专用设计建立垂直优势，Daytona 8 倍的差距就是其叙事武器。

对采购方的影响：三强博弈叠加产能紧张，意味着锁量窗口正在关闭。Intel 年内三度涨价已经发出信号——服务器 CPU 的价格曲线在 2026 年是向上的。有大批量采购计划的企业，应尽快与供应商锁定价格和交期；同时，AI 集群主机侧 CPU 的选型需要重新评估，传统"EPYC 对标 Xeon"的通用跑分逻辑，在 Vera 这类 AI 专用 CPU 出现后已不再充分。

小结​

服务器 CPU 市场的竞争维度正在迁移：从通用性能转向"AI 节点适配度"。AMD Venice 以 2nm + 256 核的量产优势延续密度路线，并借 Helios 机架实现 CPU/GPU 协同；Intel 连续三次涨价反映的是产能紧张下的议价权，而非竞争力回升；NVIDIA Vera 用 Daytona 基准 8 倍的成绩宣告 AI 专用 CPU 的独立赛道成立。对采购方而言，2026 年的关键词是"锁量"和"重估"——锁定涨价前的采购窗口，重估 AI 集群中主机侧芯片的技术选型标准。

2026 年，AI 数据中心的版图不再由网络枢纽和人口中心定义，而是由电力、主权意志和资本规模定义。从中东的 HUMAIN 到印度的 Helios，从马来西亚的 AI 云协议到东京郊外的离网电厂，一场围绕"算力主权"的全球圈地运动正在展开，而背后是超大规模厂商 6500 亿美元级别的资本开支洪流。

全球建设版图：一张不断刷新的清单​

仅最近一个月，全球 AI 基础设施的建设动态就足以拼出一张新地图：

这份清单覆盖了中东、南亚、东南亚、东亚、北美五个区域，参与者横跨芯片厂商（AMD）、云与服务器巨头（戴尔）、能源公司（Jera）、矿业转型算力公司（Bitdeer）和前沿实验室（Anthropic）——AI 基础设施已经没有"行业边界"可言。

三种主权 AI 模式​

把上面的项目归类，可以看到主权 AI 的三种典型模式：

模式一：美国盟友输出​

沙特 HUMAIN 项目采用 AMD MI355X 系统，印度由 AMD 与 TCS 将 Helios 架构本地化落地——这类项目的共同点是由美国芯片厂商输出算力架构，盟友国家提供资金、能源和市场。对美国而言，这既是出口收入，也是技术生态的扩张；对合作国而言，这是最快获得前沿算力的路径。

模式二：能源换算力​

沙特是"能源换算力"的教科书案例：用低成本能源吸引 AI 基础设施落地。日本东京郊外的项目把这一逻辑推到极致——戴尔、日本能源公司 Jera 与英国 Rhaelm 合作建设 150 亿美元、400MW 的离网 AI 数据中心，配套自建燃气发电厂，预计 2028 年运营。电力不再是电网提供的输入，而是项目自带的资产。

模式三：自研自强​

华为昇腾路线代表的是第三种模式：不受制于美国芯片供应，用自己的芯片、自己的框架构建全国算力底座。这条路门槛最高，但自主性最强。

资本开支洪流：6500 亿与 10 万亿​

主权 AI 圈地运动的燃料是超大规模厂商的资本开支。2026 年的口径已经清晰：

Amazon 一家 2026 年就计划投入约 2200 亿美元，超过很多国家一年的基建预算。而 IEEE 及行业口径给出的 10 万亿美元数据中心建设需求，说明这轮建设周期可能以十年计——这不是一个短周期投资潮，而是一场持久的基础设施重置。

离网自建电厂成为新常态​

东京 400MW 离网项目和 Oracle 用燃气卡车维持数据中心运转的新闻，指向同一个趋势：电网已经跟不上 AI 数据中心的用电增速。离网自建电厂从"备选项"变成"新常态"，原因有三：

1. 电网接入排队周期长：大型数据中心动辄数百兆瓦，接入电网的排队时间以年计；
2. 电力成本成为运营命门：Oracle 靠燃气卡车运电维持运转，说明即便是巨头也在为电力稳定性付出高昂代价；
3. 选址逻辑彻底改变：数据中心选址从"网络枢纽、靠近用户"变成"电力洼地、能源便宜"——德州 Bryan 的 ThisWay Global 73MW 设施、中东的能源换算力项目，都是这个逻辑的产物。

对芯片选型的影响也很直接：在电力受限的环境下，单位功耗的算力产出（性能/瓦）权重急剧上升，液冷、低精度推理（FP4/FP8）和 rack-scale 方案成为标配。

小结​

主权 AI 的全球圈地呈现三种模式并行：美国盟友输出（HUMAIN、印度 Helios）、能源换算力（沙特、东京离网项目）、自研自强（昇腾路线）。支撑这一切的是 6500 亿美元级的年度 capex 和 10 万亿美元级的长期建设需求。最深刻的结构性变化是选址逻辑：从网络枢纽转向电力洼地，离网自建电厂成为新常态，Anthropic 自建数据中心则说明前沿实验室也在绕开云厂商直接下场。对从业者而言，评估 AI 基础设施项目的第一问已经从"带宽够不够"变成了"电从哪来、多少一度"。

财报季密集报喜：台积电 Q3 营收约 NT$1.49 万亿创历史新高，三星 Q3 营业利润同比大增近 8 倍，12 层 HBM4E 已通过 NVIDIA 质量验证——AI 算力的利润池正在向存储环节大规模迁移。

财报季：台积电、三星双双创纪录​

据路透与 DIGITIMES 10 月 8 日至 9 日的报道，财报季传来一连串超预期数据：

• 台积电：Q3 营收约 NT$1.49 万亿，创历史纪录并超出市场预期，AI 需求为主要驱动力；其中 9 月单月营收约 NT$5118.6 亿，同比增长 54.6%；
• 三星电子：Q3 营业利润预计超 100 万亿韩元，同比大增近 8 倍，HBM 与 AI 存储需求爆发是核心推手。

代工与存储同步创新高，说明这一轮景气并非单一环节的结构性紧张，而是 AI 算力全链条的需求爆发。

三星：HBM4E 通过验证，下一代路线图发布​

三星在产品层面有两个关键动作：

• 下一代 12 层 HBM4E 已通过 NVIDIA 及主要超大规模客户的质量验证，为后续放量铺平道路；
• 发布下一代 AI 存储路线图，包括 zHBM 与 400 层以上 V10 NAND 技术。

HBM4E 通过 NVIDIA 认证，意味着三星在 HBM4 世代的竞争中拿到了进入下一轮的门票。在 AI 存储这个增长最快的细分市场，三星与 SK 海力士的正面交锋还将继续，而 zHBM 与 400 层以上 V10 NAND 的路线图，则表明存储厂商的技术竞赛已经延伸到两个世代之后。

封装与设备：产能稀缺的另一面​

存储之外，产业链上下游同样动作密集：

• GlobalFoundries 与台积电签署多年期 20 亿美元协议，将在其美国 Malta 工厂为台积电 CoWoS 生态生产硅 interposer——两大代工对手互供，属于罕见安排；
• Applied Materials 与 Intel 扩大合作，聚焦下一代互连扩展与 Foveros 3D 技术；
• ASML 与 ZEISS 表示，下一代光刻技术（High-NA 之后）可能还需十年才会到来。

GF 为台积电生产 interposer 尤其值得玩味：在先进封装产能全面紧张的当下，封装环节的稀缺程度已经超过代工环节的竞争——连对手之间也要互相借产能，这正是 CoWoS 类先进封装供不应求的最直观注脚。

内存挤压传导至 AI PC​

DIGITIMES 分析指出，AI PC 正面临内存挤压：在内存厂商的优先级中，服务器 DRAM 需求被放在首位，AI PC 依赖的 LPDDR5X 供给承压。刚刚开启预订、最高配备 128GB 统一内存的 Surface Laptop Ultra，正是这一矛盾的直接体现——AI PC 想要的内存容量越大，与服务器需求的冲突就越尖锐。

美光此前已预测，NAND 与 DRAM 短缺将持续至 2028 年。存储缺货不是短期波动，而是一个跨越数年的结构性周期。

分析：利润池正在迁移​

第一，利润从加速器向存储迁移。"没有分配到 HBM 的 AI GPU 是库存而不是算力"——这句话正在成为行业共识。GPU 再强，没有 HBM 就出不了货，存储环节因此获得了整个 AI 供应链中最强的话语权之一。三星营业利润暴增近 8 倍，就是利润池迁移最直接的证据。

**第二，HBM 定价权回归。**SK 海力士、三星、美光正迎来十年来最强的定价地位。HBM 与 AI 存储的溢价正在重塑存储厂商的盈利结构，也推高了所有 AI 芯片的成本曲线。

**第三，封装产能比代工竞争更稀缺。**GF 与台积电的互供协议说明，当先进封装产能不足时，代工竞争可以让位于产能协作。对芯片厂商而言，封装与 HBM 配额正在成为出货的前提条件。

**第四，对采购方的影响。**HBM 配额、DRAM 供给优先级都在向服务器和 AI 基础设施倾斜，终端设备的内存配置与成本将长期承压。这也与此前的国产芯片涨价潮相互呼应——存储成本上涨正在沿着供应链向所有 AI 算力产品传导。

小结​

台积电 Q3 营收约 NT$1.49 万亿、三星营业利润大增近 8 倍、12 层 HBM4E 通过 NVIDIA 认证、GF 为台积电代工 interposer——这一轮财报季确认了一个事实：内存超级周期已全面爆发，AI 算力的利润池正在加速向存储与封装环节迁移。对芯片厂商而言，HBM 配额就是出货许可证；对采购方而言，锁定存储供给正在成为与锁定 GPU 同等重要的战略动作。

2026年第41周（9月28日—10月6日前后），AI芯片行业密集事件爆发：NVIDIA N1X冲击PC市场、Intel年内第三次涨价、AMD Helios量产、MLPerf新纪录、存储新范式、国产涨价与上市潮。本篇按国际、国产、存储与系统、资本与市场四节汇总。

国际动态​

NVIDIA N1X发布（10-04）：NVIDIA发布N1X PC处理器，直接竞争Intel与AMD的PC处理器市场，当日两家股价各下跌4.2%。N1X基于RTX Spark芯片、与微软合作打造，2026年秋季上市。

Intel CPU涨价10%（10-05生效）：这是Intel自2025年以来的第三次涨价，受AI需求和产能紧张驱动。

AMD Helios量产（9-18报道）：MI455X首批出货目标Q3末，OpenAI 6GW、Meta 6GW、Anthropic合作兑现中，微软为首批客户之一。

MLPerf Inference v6.1（9-16）：Vera Rubin NVL72首秀，跑Qwen3-VL较GB300最高提升3.7倍；AMD MI350以512卡创下575万tokens/秒的纪录。

国产动态​

华为昇腾950：智算集群云服务9月30日国内商用，11月30日全球商用；昇腾960超节点引入NPO技术、支持4096卡、提供8E FP8算力。

平头哥真武V900（9-22云栖大会）：216GB显存、1200GB/s带宽，2027年Q1量产；同期发布倚天720/730 CPU路线图。

国产芯片涨价（路透）：寒武纪690与昇腾950DT涨价20%-50%，HBM成本上涨是主要驱动。

燧原科创板上市（9-11）：开盘上涨188.37%，市值达1764亿元。

摩尔线程"庐山"：年底亮相，3A渲染性能提升15倍、光追50倍、AI 64倍。

存储与系统​

SK海力士：9月17日发布HBF/PIM/eSSD/SALT-KV组合，9月18日成立SK hynix Ventures投资生态；美光9月15日发布超密度服务器内存模组；AWS Annapurna×NVIDIA推进NVHBM定制内存；长鑫存储据路透报道筹备进军NAND。

电网与能效：Emerald AI、Google、NVIDIA于9月16日成立AEMA（先进能源与算力联盟）；NVIDIA DSX MaxLPS助力Lambda实现同功率下token吞吐+24%、每瓦性能+23%。

资本与市场​

份额格局：据Counterpoint口径，国产AI芯片从2022年的近乎零份额，到2025年已达41%；其中华为昇腾约占国产市场的62%。

股价与估值：同期美股芯片板块上涨，NVIDIA收涨2.54%、AMD涨超6%。

下周关注​

1. 昇腾950云服务全球商用倒计时：11月30日全球商用节点临近，海外部署进展值得跟踪；
2. Helios首批交付：MI455X能否兑现Q3末首批出货目标；
3. Q4国产新卡发布窗口：年底前后国产厂商新品密集期，摩尔线程"庐山"亮相在即。

小结​

第41周的主线是"三重加速"：算力侧（N1X、Helios、MLPerf新纪录）节奏空前，存储侧（HBF、NVHBM、SALT-KV）范式更新，供给侧（Intel涨价、国产涨价20%-50%）紧张加剧。国产份额41%的数据说明格局重塑已在发生，Q4将是验证兑现能力的关键窗口。

2026年进入第四季度，AI芯片竞争的关键词从"发布"转向"交付"。Rubin能否持续放量、Helios能否如期爬坡、昇腾950DT如何定价上市，将共同决定2027年竞争格局的起点。

NVIDIA：Rubin放量与生态开放双线推进​

Q4期间NVIDIA的计划主线：

• Vera Rubin NVL72：2026下半年持续放量，MLPerf Inference v6.1首秀已登顶（Qwen3-VL较GB300最高3.7倍），HBM4平台优势开始兑现；
• N1X：基于RTX Spark的PC处理器按计划2026年秋季上市，打开消费级战场；
• Blackwell Ultra（B300）：租用价格参考Nebius口径约9.50美元/GPU小时，仍是当前租赁市场的重要基准；
• 后续代际：Rubin Ultra等后续路线待发；
• 生态动作：NVLink Fusion持续开放生态，NVHBM定制内存方案推进。

AMD：Helios从首发出货到Q4爬坡​

AMD在Q4的核心任务是交付：

• Helios机架：MI455X首批出货目标Q3末，Q4进入量产爬坡阶段；
• 客户部署：OpenAI 6GW、Meta 6GW部署合作推进中，微软作为首批客户计划2026年下半年交付；
• MI430X：驱动欧洲LUMI-AI超算，拓展科学计算场景；
• ROCm：软件生态继续补齐；
• 下一代：Helios II / MI500级产品路线待公布。

华为：昇腾950DT上市与云服务全球商用​

华为Q4的关键节点最为明确：

• 昇腾950DT：Q4上市，报价超25万元；
• 昇腾950智算集群云服务：9月30日已国内商用，11月30日全球商用；
• 960系列：计划2027年接棒，970/980排在2028-2029年。

阿里平头哥：真武V900量产倒计时​

平头哥的时间表指向2027年：真武V900计划2027年Q1量产上云，配套磐久AL128与50万卡集群规划；J900排期2027年Q3。Q4将进入量产前最后的验证阶段。

OpenAI/博通 Jalapeño：多吉瓦部署推进​

OpenAI与博通合作的Jalapeño定制芯片规格已明确：13.4 PFLOPS（4-bit精度）、232GB内存，多吉瓦部署规划正在推进。这枚自研芯片的量产进度，将直接影响OpenAI未来的算力自给率。

关键变量：三大约束​

Q4的交付兑现程度，将取决于三个外部约束：

1. HBM供给：戴尔CEO警告2027年可能比2026年更紧缺，HBM产能是所有GPU路线图的共同瓶颈；
2. 国产涨价传导：昇腾950DT涨价20%-50%、寒武纪690涨价20%-30%（路透，HBM成本驱动），涨价将传导至国产算力服务价格；
3. 电力约束：Emerald AI/Google/NVIDIA成立的AEMA电网响应模式，预示电力正在成为算力扩张的第一性约束。

三条观察建议​

基于上述事实，给三类角色的观察点（非投资建议）：

• 采购方：昇腾950DT与寒武纪690的涨价幅度表明国产算力已进入卖方市场，锁量谈判宜早不宜迟；同时关注Helios Q4实际爬坡数据，作为第二供应源评估依据；
• 开发者：ROCm生态补齐与NVLink Fusion开放，意味着2027年异构算力混布的软件门槛正在降低，可提前在推理侧做多框架适配；
• 投资者：可跟踪的公开观察点包括——Helios首批交付兑现情况、昇腾950云服务11月30日全球商用落地、HBM价格走势对各家毛利率的影响信号。

小结​

2026年Q4是"交付验证季"：NVIDIA Rubin放量、AMD Helios爬坡、昇腾950DT上市与云服务全球商用、平头哥V900量产倒计时——各家计划均已排定，剩下的变量集中在HBM供给、涨价传导与电力约束三点。所有时间节点以"计划/预计/排期"口径为准，Q4末回看兑现率，就是对2027年格局的最好预判。

The Tuesday-afternoon AI session at Hot Chips 2026 this August was the most historically significant of the conference — not because any single chip was so powerful, but because almost everything on stage was a "hyperscaler de-NVIDIA-ization" custom ASIC: Google's 8th-gen TPU, OpenAI's first self-designed chip, Microsoft Maia, Meta MTIA, and Cerebras wafer-scale racks, all on one stage. When the world's largest AI compute buyers start treating GPUs as "one of the options," the power structure of AI hardware is loosening.

1. OpenAI Jalapeno: Building a Chip in 9 Months​

On June 24, 2026, OpenAI, together with Broadcom, unveiled its first self-designed inference ASIC, Jalapeno — the fifth member of the "custom inference chip club."

The talk title "You Can Just Build Things … Chips" is itself a signal: the largest AI compute buyer no longer defaults to GPU as the only path.

2. Google TPU v8: The Biggest Architectural Pivot in a Decade — Train/Infer Split​

Google has the longest custom-chip history (2016 to now), and its 8th-gen TPU for the first time splits the product line in two:

On capacity, Morgan Stanley estimates based on supply-chain interviews that Google TPU production in 2026 may exceed 3 million units (a brokerage estimate, not an official target). Google is also the only vendor to achieve large-scale custom-chip deployment and sell compute externally (Gemini runs on TPUs).

3. Meta MTIA: From Recommendation Systems to a GenAI Dual Mission​

Meta's custom journey has the clearest starting point — MTIA was originally built for recommendation ranking hardware and is being pulled toward a dual mission by generative AI.

• MTIA 300 is deployed; 400 / 450 / 500 are planned at roughly one new model every 6 months through 2027;
• Based on RISC-V, Meta claims up to 25× compute gain;
• Node evolves with industry cadence: 100 (7nm) → 200 (5nm) → 300 series (3nm + CoWoS);
• In partnership with Broadcom; another chip codenamed Iris reportedly passed testing in July 2026;
• Meta plans to start volume production of one of them in September 2026, doubling its overall compute.

4. Microsoft Maia 200/300: Most Advanced Deployment​

Microsoft's Maia 200, released January 26, 2026, is the most advanced in deployment among the four:

Microsoft claims roughly 3× the performance of Amazon's Trainium on specific benchmarks. The short-term strategy is a dual track of "self-designed Maia + purchased NVIDIA" in parallel — self-designed chips need time from design to mass production, and NVIDIA's mature ecosystem cannot be replaced in the short term.

5. Amazon Trainium 3 and Anthropic's In-House Team​

• Amazon: The Trainium series is already commercial, with 1.4 million units cumulatively deployed (officially disclosed) — a multi-billion-dollar business; its strength is the AWS customer base, letting enterprises choose between NVIDIA GPUs and self-designed chips. Trainium 3 continues this path.
• Anthropic: In August 2026 announced the formation of an in-house chip team, with no tape-out or mass-production timeline yet; initially positioned as a complement (not a replacement) to existing partnerships with NVIDIA/AMD/AWS/Google Cloud, aiming to tailor-build for the Claude architecture and shed reliance on a single GPU.

6. NVIDIA's Answer: Not a Faster GPU, But Full-Stack​

It's easy to simplify the narrative to "four companies build chips, NVIDIA defends GPU." But NVIDIA took 6 slots at Hot Chips: a RISC-V tutorial, the Vera CPU, the Rubin GPU, the BlueField-4 DPU, the Spectrum-X multi-plane network, and an LPU accelerator.

A hyperscaler ASIC replaces only one of those five pillars. If the CPU, NIC, switching fabric, and software all come from the same vendor, what you save by swapping out the accelerator is far less than the accelerator line item on the bill suggests. Rubin's play is a full-stack AI factory platform spanning seven chips and five racks — the competitive answer is "full-stack positioning," not "a faster single chip."

7. Trend Judgment: Inference De-GPU-izes, Training Still GPU-Led​

• Inference side: The CUDA moat visibly shallows. Inference is parallelizable and replaceable at the endpoint; custom ASICs trade away the generality tax (implementing only the operations LLMs actually execute) for lower cost/token. Groq LPU, Cerebras, and various TPU/ASIC players all compete on the same metric.
• Training side: Foundation models are still trained on GPUs, with no serious challenger in the short term. NVIDIA's three training moats (fastest silicon + NVLink + CUDA) remain firm.
• Conclusion: Custom chips are not "replacing NVIDIA," but giving buyers a credible external negotiation option in the largest and fastest-growing battlefield — inference. That alone is enough to reshape the economics of AI infrastructure.

Related Links​

• Inference Accelerator Market 2026
• Hot Chips 2026 Full Recap
• Google TPU 8t Spec Page
• Google TPU 8i Spec Page

References​

• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim
• Custom AI inference silicon: why OpenAI built Jalapeno - nexi.fund
• Anthropic Builds Custom AI Chips for Claude - Studio Global AI
• 所有大厂都在做同一件事：自己造芯片，少买英伟达的 - Toutiao

This article is compiled from August 2026 Hot Chips on-site reports, corporate announcements, and industry analysis. Some capacity and performance figures are brokerage estimates or vendor-disclosed figures; actual results are subject to mass-produced products.

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

• Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
• HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
• Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

• 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
• The industry already anticipates significant price increases;
• For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

Related Links​

• NVIDIA Rubin Spec Page
• AMD MI455X Spec Page
• Hot Chips 2026 Full Recap

References​

• Samsung's HBM4 Yield Hits 80% as HBM Race Heats Up - TrendForce
• Samsung HBM4 Yield Hits 80%, Boosting AI Memory Supply - PC Central
• Samsung Weighs Shipping Legacy Memory Backend to Vietnam to Unlock HBM Capacity - TechTimes
• 芯闻|六个月良率跃迁：三星HBM4突破80%黄金门槛 - Toutiao

This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

In 2026, China's AI chip market landscape has shifted from "NVIDIA unipolar dominance" to "overseas vendors leading, domestic multi-route catch-up." According to industry research, China's overall AI accelerator market was ~4M units in 2025, of which 1.65M were domestic, with share first breaking 40%; as products iterate and fabs follow up, the localization rate is expected to rise to 60%-70% by 2027. This article focuses on the latest H2 2026 progress of Huawei Ascend, Cambricon, and Moore Threads — the domestic "Big Three."

1. Huawei Ascend: 950 Capacity Fully Booked, 960 Roadmap Unveiled​

Ascend's core advantage is "architecture + full-stack ecosystem synergy," with ~800K units shipped in 2025, capturing 50% of the total domestic vendor share. The product iteration cadence is clear:

950 series capacity has entered a "fully booked" state: 950PR entered mass production in April 2026; June monthly capacity jumped to 500K-600K units (nearly 10x MoM), with a full-year target of 1.2M units at 100% certainty; ByteDance locked in 350K units for $5.6B, while Tencent / Alibaba / Baidu combined locked in 400K units.

Ascend 960 roadmap specs (per roadmap disclosure):

The previous-gen Ascend 384 super-node has cumulatively shipped over 750 sets, deployed across 20+ industries including internet, operators, finance, education, and healthcare — Huawei calls it "the only domestic super-node that has trained a SOTA model."

2. Cambricon MLU690: H2 Mass Production, Entering ByteDance Bidding Window​

Cambricon is the core domestic compute leader in the absence of an Ascend IPO, with the technology gap continuously narrowing:

• Siyuan 590 (7nm): Performance equivalent to 80% of A100, already supports DeepSeek, continuously adapting to mainstream large models like Qwen 3 and GLM
• Siyuan 690 series: Will enter mass production in H2 2026, expected to achieve order scale-up during ByteDance's H2 bidding window
• Revenue certainty: Equity incentive targets show >100% revenue growth for the next 3 years: 2026 revenue target 13.5B RMB, 2027 27B RMB, 2028 60B RMB

Cambricon fully benefits from the industry dividend of "domestic CSP capex + full adaptation of domestic large models and domestic chips," making it the most direct elasticity play on rising localization rate.

3. Moore Threads MTT S5000: Full-Function GPU + Ecosystem Breakthrough​

Moore Threads takes a differentiated "full-function GPU" route, with the flagship MTT S5000 based on the 4th-gen "Pinghu" MUSA architecture:

Its engineering capability is verified: the Kuae (KUAE) intelligent computing cluster based on S5000 achieves 95% training linear scaling efficiency, with compute efficiency loss within 5% at ten-thousand-card scale; supports checkpoint-resume training with effective training time ratio >90%; and has trained a MoE-236B base model with >25 trillion tokens of corpus from scratch.

The ecosystem is Moore Threads' deepest moat: MUSA has achieved 100% core math library compatibility, 3000+ PyTorch operator compatibility, covers 55 categories of core AI operators, has official vLLM and SGLang support, Day-0 adaptation of mainstream models, and 800K+ developers. Its PD heterogeneous-disaggregation solution achieves equivalent replacement of international high-end GPUs at a 2:1 ratio with S5000, significantly reducing inference cost.

The 5th-gen "Huagang" architecture (released 2025-12) supports FP4 to FP64 full precision, with 50% higher compute density and 10x better energy efficiency than the previous gen, supporting 100K+ card clusters; cumulative R&D investment in the "Huashan" (train-infer integrated) and "Lushan" (graphics rendering) new chips based on this architecture exceeds 900M RMB.

4. Software Ecosystem Decides: Day-0 Adaptation Becomes Routine​

Beyond hardware, software ecosystem realization is the watershed for domestic compute in 2026:

• Huawei's CANN heterogeneous computing architecture and MindSeries suite are fully open-sourced, with the community incubating 67 projects, 12.44M+ lines of code, and 3,500+ monthly active developers
• The "release-and-adapt" closed loop between domestic large models and domestic chips has basically formed: Tencent Hunyuan T3 (295B), DeepSeek-V4, and GLM-5.2 all completed Day-0 adaptation
• 2026 is regarded as the "first year of domestic super-nodes"; Huatai Securities estimates China's super-node architecture market will reach 341.4B RMB by 2028, with a 2026-2028 CAGR of 194%

5. Industry Judgment: From "Can It Be Built" to "Can It Be Used Well"​

The domestic Big Three are converging along three paths:

1. Huawei: Locks government/enterprise and internet big customers with super-node system-level capability + full-stack software
2. Cambricon: Impacts the revenue inflection point by narrowing the training-side gap + scaling up via big-customer bidding
3. Moore Threads: Covers cloud-edge-end full scenarios with full-function GPU generality + mature CUDA-compatible ecosystem

The common shortcoming of all three remains advanced process and HBM supply — precisely the core link of overseas controls. But as domestic HBM iterates and fabs follow up, a realistic path to 60%-70% localization by 2027 exists.

Related Links​

• Huawei Ascend 960 spec page
• Huawei Ascend 950DT spec page
• Cambricon MLU690 spec page
• Moore Threads MTT S5000 spec page

References​

• Domestic AI Chip Industry View Update - Robo Datayes
• Moore Threads, Two Positives in One Day - Eastmoney
• Moore Threads × SiliconFlow: PD Disaggregation Heterogeneous Compute Co-location Whitepaper - EE Focus
• After Approaching Break-even, Moore Threads Faces Hong Kong "Big Exam" Again - Top News

This article is compiled from public industry research, broker views, and corporate announcements as of August 2026. Some shipment and market-share figures are third-party estimates, not officially confirmed data.