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AMD Instinct AI accelerators

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AMD Advancing AI 2026 Opens Tomorrow: Three CDNA5 MI400 Models, Helios Rack Hits 3 exaFLOPS, OpenAI + Meta Lock 12GW Deal

· 4 min read
AI Hardware Analyst

AMD has confirmed its flagship AI event Advancing AI 2026 will be held July 22-23, 2026 at the Moscone Center in San Francisco, with the keynote on July 23 hosted by Chair and CEO Lisa Su. The event will complete the Instinct MI400 series availability timeline, pricing, and independent benchmark data.

1. Instinct MI400 family: three CDNA 5 accelerators

AMD fully revealed the MI400 matrix at CES 2026; all three accelerators use CDNA 5 architecture, TSMC 2nm process, differentiated by precision and scenario:

ModelPositioningKey specs
MI455X (flagship)Large-scale train/inference (rack-scale)320B transistors, 12 chiplets, 432 GB HBM4 (12×36GB), 19.6 TB/s, FP4 40 PFLOPS / FP8 20 PFLOPS
MI440X (enterprise)Local enterprise AI (8-card node)Low-precision AI (FP4/FP8/BF16), direct MI300/MI350 replacement, compatible with existing power/cooling
MI430X (HPC/sovereign AI)High-precision scientific computing + AIFull FP32/FP64, already deployed at Oak Ridge Discovery and France's first exascale Alice Recoque

MI455X and MI440X target low-precision AI (FP4/FP8/BF16); MI430X fills traditional HPC high-precision needs — improving energy efficiency and cost-performance by "trimming execution units by precision." All three support UALink (among the first accelerators compatible with the standard) and Infinity Fabric die-to-die interconnect; rack scaling uses Ultra Ethernet.

Lisa Su confirmed on the Q1 2026 earnings call: MI455X samples have been sent to core customers, with demand "exceeding the company's internal expectations for 2027."

2. Helios rack: 3 exaFLOPS per cabinet

AMD enters the hyperscale market with the Helios rack-scale platform:

MetricHelios rack
Accelerators72 × MI455X
Aggregate HBM431 TB
Total memory bandwidth1.4 PB/s
Per-cabinet computeUp to 3 AI exaFLOPS (Q3 delivery target)
Target customersHyperscale train/inference clusters

Helios uses AMD's in-house Zen 6 EPYC Venice CPU (18 per rack) + Pensando Vulcano 800G NIC, integrated via the open ROCm software stack; AMD also plans a double-width 128-card Helios variant, pushing per-cabinet compute to the 3 AI exaFLOPS ceiling. Further out, the MI500 series (CDNA 6, 2nm, HBM4E) is planned for 2027, with official claims of up to 1000× AI performance vs MI300X.

3. 12GW deal: OpenAI + Meta dual endorsement

AMD holds two historic-scale compute agreements totaling about 12 GW, with lifetime potential revenue possibly reaching $100B:

CustomerScaleFirst deploymentStructure
OpenAI6 GW (multi-gen products)First 1 GW, H2 2026 on MI450"compute-for-upside": up to 160M warrants, vesting by milestone and stock-price targets
Meta6 GWCustom MI450 chips, from H2 2026Deployed in next-gen data centers

Financial expectations

Metric2026 forecast
MI400 series revenue~$7.2B (about 25% of data-center sales)
Data-center GPU revenue~$15B (up +114% YoY)
Total data-center revenuePossibly $28.7B (up +73% YoY)

⚠️ Execution risk: AMD has flagged that MI450's Q3 mass production will weigh on gross margin (new products below company average); advanced process and advanced packaging (TSMC CoWoS) capacity remain the main constraint.

Industry interpretation

  1. CUDA moat being pried open: when companies building the world's largest training clusters — Meta, OpenAI — bet on AMD silicon, AMD's long-standing 5-7% GPU share ceiling is being broken.
  2. Memory advantage as differentiation: 432 GB HBM4 / 19.6 TB/s vs NVIDIA Rubin's 288 GB offers capacity advantage, critical for large-model inference (KV Cache-constrained scenarios).
  3. Tight benchmarking pace: MI450 and NVIDIA Vera Rubin both ramp in H2 2026, with the two giants competing head-on over HBM4 supply and CoWoS capacity.

References


This article was written on the eve of Advancing AI 2026 (July 22-23, opening tomorrow); the keynote is July 23 hosted by Lisa Su, where MI400's final availability, pricing, and independent benchmarks will be revealed — we will update in sync.

AMD MI455X Stuns at CES 2026: AI Chip Performance Up 1000x in 4 Years

· 6 min read
Industry Research Team

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights

  • MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
  • MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
  • Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
  • Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
  • Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
  • Architecture upgrade: from CDNA 4 to CDNA 5
  • Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

ModelPositioningMemoryFP4 computeFP8 computeTDP (est.)
MI455XFlagship training+inference432GB HBM440 PFLOPS20 PFLOPS~1,000W
MI450Cost-performance training288GB HBM428 PFLOPS14 PFLOPS~800W
MI440XEnterprise inference216GB HBM425 PFLOPS12.5 PFLOPS~600W
MI430XHPC / scientific computing192GB HBM420 PFLOPS10 PFLOPS~500W
MI400XGeneral / edge inference128GB HBM412 PFLOPS6 PFLOPS~400W

Key upgrades (vs MI350 series):

  • Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
  • Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
  • Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +)
  • Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
  • Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X

MetricMI355X (2025)MI455X (2026)Improvement
FP4 compute20 PFLOPS40 PFLOPS
FP8 compute10 PFLOPS20 PFLOPS
Memory capacity288GB HBM3e432GB HBM41.5×
Memory bandwidth8 TB/s19.6 TB/s2.45×
ProcessTSMC 3nm2nm + 3nm hybridNew gen
ArchitectureCDNA 4CDNA 5New gen
TDP800-1000W~1,000WFlat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades

  1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
  2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
  3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
  4. Native sparsity support: MoE Expert-Parallel optimization
  5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin

MetricAMD MI455XNVIDIA B200NVIDIA Rubin R200 (2026 Q4)
FP4 compute40 PFLOPS20 PFLOPS (45 sparse)~40 PFLOPS (est.)
FP8 compute20 PFLOPS10 PFLOPS (22.5 sparse)~20 PFLOPS (est.)
Memory432GB HBM4192GB HBM3e288GB HBM4
Memory bandwidth19.6 TB/s8 TB/s13 TB/s
TDP~1,000W700-1000W~1,000W
Process2nm + 3nm hybridTSMC 4npTSMC 3nm
Mass production2026 Q42024 Q42026 Q4
Software ecosystemROCmCUDACUDA
StrengthMemory capacity, open ecosystemMost mature ecosystemNext-gen architecture
WeaknessSoftware ecosystem gapSmaller memoryNot yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline

TimeEvent
June 12, 2025MI400 series specs first announced at Advancing AI
January 5, 2026MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3MI450 sampling begins
2026 Q4MI455X mass production
2026 Q4MI440X (enterprise inference) launched
2027 Q1MI430X/MI400X (HPC/edge inference) launched
2027MI500 series (next gen)

AMD AI chip roadmap (2025-2027)

TimeProductProcessNotes
Q4 2024MI325XTSMC 5nmHBM3e upgraded
Q3 2025MI355X (MI350 series)TSMC 3nmCDNA 4, 288GB HBM3e
Q4 2026MI455X (MI400 series)2nm + 3nm hybridCDNA 5, 432GB HBM4
Q1 2027MI500 seriesTSMC 2nm (est.)Next gen, further gains

Software ecosystem: ROCm's progress and challenges

✅ Progress

  • PyTorch 2.5+: native MI300X/MI455X support
  • Hugging Face Transformers: official AMD GPU support
  • vLLM 0.8+: MI300X inference support (experimental)
  • JAX: AMD adapting (vs Google TPU)

⚠️ Challenges

  • Framework optimization: PyTorch on AMD GPUs still below NVIDIA
  • Operator coverage: some niche operators need hand-written HIP
  • Multi-card communication: RCCL (vs NCCL) still lags
  • Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison

VendorProductFP4 computeMemoryMass productionStrengthWeakness
AMDMI455X40 PFLOPS432GB HBM42026 Q4Largest memory, open ecosystemSoftware gap
NVIDIAB20020 PFLOPS192GB HBM3e2024 Q4Most mature ecosystemSmaller memory
NVIDIARubin R200~40 PFLOPS288GB HBM42026 Q4Next-gen architecture, CUDAExpensive
HuaweiAscend 910C~1.6 PFLOPS64GB HBM2026 Q2China-localizedExport-controlled
GoogleTPU 8t~9.2 PFLOPS~256GB HBM3eLate 2027Gemini-integratedGoogle Cloud only

Industry impact

1. Impact on NVIDIA

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

  • NVIDIA has the CUDA ecosystem moat
  • NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
  • AMD only sells cards/nodes, NVIDIA sells AI factories
  • MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

  • Catch up to 5nm + HBM3e by 2026-2027
  • Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers

MI455X gives cloud providers a second option beyond NVIDIA:

  • Microsoft Azure: already deployed MI355X, may follow with MI455X
  • Google Cloud: in-house TPU, won't use AMD
  • Amazon AWS: in-house Trainium/Inferentia, won't use AMD
  • Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

References


This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).