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AMD Instinct MI400 series

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AMD Helios 量产爬坡确认:从 MI455X 规格到 6GW 大单的完整拼图

· 3 min read
Industry Research Team

10 月上旬,AMD 在 OCP 2026 场边确认:Helios 机架级 AI 平台的量产、交付与验证正在进行,OpenAI、Meta、微软和 Oracle 的站点已有初始系统安装运行。距离 7 月 23 日 MI455X 正式发布不到三个月,AMD 第一次在机架级产品上跑赢了「发布即交付」的节奏。

MI455X 规格速览(官方口径)​

项目参数
架构CDNA 5,TSMC 2nm 计算芯粒 + 3nm I/O 与缓存芯粒
显存432 GB HBM4(12 颗堆栈),带宽最高 23.3 TB/s
FP4 算力40.3 PFLOPS(OCP MXFP4 稠密)
FP8 算力20.1 PFLOPS
互联UALoE scale-up 3.6 TB/s + UALink scale-out 600 GB/s
量产2026 Q3 末出货,H2 2026 至 2027 爬坡

机架级:一台 Helios 装 72 颗 MI455X + 18 颗 EPYC Venice CPU,总显存 31TB HBM4,峰值 FP4 2.9 EFLOPS。AMD 估算同测试条件下 Helios 每美元 Token 产出可比 NVIDIA Vera Rubin NVL72 高约 30%(AMD 建模口径,采用预估价格,非实测)。

需求基本盘:三笔吉瓦级协议​

客户协议规模节奏
OpenAI6 GW 多代协议(首期 1 GW MI450)2026 H2 开始部署,2027 加速;附最高 1.6 亿股认股权证
Meta6 GW、五年期2026 H2 起首批交付
Anthropic最多 2 GW MI450 系列2026-10-06 官宣,已在使用 MI355X
Oracle OCI5 万颗 MI450 SuperCluster2026 Q3 启动,2027 扩容
微软 AzureND MI455X v7 虚拟机2026-07 宣布

加上 9 月底 HPE 宣布的 12 亿美元 Vultr Helios 整机订单,MI450 系列的需求能见度已经排到 2027 年。

争议点:量产节奏的两个版本​

今年年中曾有一份 SemiAnalysis 报告称 2026 年只有工程样片与小批量、大规模爬坡推迟到 2027 Q2。AMD 高管公开否认,坚持 MI455X 按 H2 2026 交付目标推进;8 月 4 日 Q2 财报(营收 115 亿美元,数据中心 67 亿美元同比 +107%)中 Lisa Su 的表述是「Instinct 部署规模化、Helios 开始爬坡」。

两个口径其实兼容:首批 Helios 机柜确实在 2026 下半年交付给了发布客户,但企业级可批量采购的量大概率是 2027 年的话题。计划 2027 年扩容的团队,现在就可以把 Helios 纳入与 Vera Rubin NVL72 并列的评估清单。

与 NVIDIA 的真实差距​

纸面规格上,MI455X 在显存容量(432GB 对 288GB)与单机架 FP4 上有优势;差距在两点:一是机架级生态的成熟度——NVIDIA 的 NVL72 已规模出货多个季度而 Helios 刚开始爬坡;二是 ROCm 软件栈在大规模生产环境的验证广度。AMD 的策略是用「开放标准(UALink/UALoE)+ 更大显存 + 更低单 Token 成本」在 2027 年的采购决策里换到真实份额。

相关阅读​

AMD 数据中心业务的增长曲线:从追赶者到第二供应商

· 4 min read
Industry Research Team

在英伟达统治AI算力的年代,"第二供应商"不是一个安慰奖,而是一个真实的市场缺口——云厂商们迫切需要一个可以议价的备选项。AMD正在用数据中心业务的增长曲线证明,这个席位它不仅拿到了,而且开始变现。

增长曲线:数据中心收入站稳43亿美元​

2025年第三季度,AMD交出创纪录的92亿美元季度营收,同比增长36%。其中数据中心业务收入43亿美元,同比增长22%,环比增长34%,主要由第五代EPYC处理器和Instinct MI350系列GPU的强劲需求驱动。前三季度数据中心累计收入113亿美元,同比增长29%。

值得注意的一个细节是:AMD数据中心业务的营业利润率在25%左右,明显低于英伟达约七成的整体毛利率。这既是追赶者为撬开市场付出的价格让利,也意味着一旦MI400世代放量、产品组合改善,AMD的利润弹性会比收入弹性更可观。

AMD 2025年第三季度关键数据数值同比变化
总营收92亿美元增长36%
数据中心收入43亿美元增长22%
客户端业务收入28亿美元增长46%
数据中心前三季度累计113亿美元增长29%
Q4营收指引约96亿美元增长约25%

从卖芯片到卖机架:OpenAI与Oracle的两个订单​

真正改变AMD叙事的是两个大单。其一是与OpenAI达成的多年期战略合作:OpenAI将部署6吉瓦的AMD GPU,首批1吉瓦的Instinct MI450部署计划于2026年下半年启动,公司预计该合作未来几年可产生超过1000亿美元的收入。其二,Oracle云将率先上线基于AMD"Helios"机架设计的公共AI超算集群,搭载MI450 GPU、EPYC "Venice" CPU与Pensando "Vulcano"网络方案,首批5万卡于2026年第三季度部署。

Helios机架级方案的意义在于:AMD第一次以整机架形态、支持Meta主导的开放机架宽版规范参与竞争,把竞争从"单卡性价比"升维到"集群总拥有成本"。美国能源部的Lux AI超算选用MI355X、2028年交付的Discovery超算选用MI430X,则进一步巩固了其在主权与科学计算场景的背书。软件侧,ROCm 7的发布持续填补其与CUDA之间最被诟病的生态差距。

追赶的代价:出口管制的账单​

AMD的增长曲线并非没有断点。由于美国出口管制,Instinct MI308对华出货没有产生任何收入,公司还因此在2025年第二季度计提了约8亿美元的库存及相关减值——这笔账单直接压低了当季毛利率,也解释了为什么AMD财报中对华业务始终保持"零假设"的谨慎口径。

从节奏上看,AMD把宝押在MI400世代:MI450负责2026年下半年起的通用AI算力放量,MI430X主攻主权AI与HPC,两者配合Helios机架形成组合拳。管理层对第四季度约96亿美元的指引(不含对华收入)表明,即便在出口管制阴影下,增长轨道依然陡峭。

研判:第二供应商的席位价值才刚开始定价​

AMD的故事本质上是"结构性看涨期权":EPYC在服务器CPU市场持续蚕食份额提供基本盘,Instinct则在大客户急于分散供应链的窗口期完成卡位。6吉瓦协议与千亿美元收入预期仍需数年兑现,中间隔着产能、良率、ROCm生态成熟度三道坎;但只要云厂商的"去单一化"诉求存在,AMD的数据中心曲线就有托底。对产业观察者而言,2026年下半年MI450的实际交付节奏,将是检验这份叙事成色的第一个硬指标。

MI400 系列盘点:MI430X 驱动欧洲 LUMI-AI 超算,AMD HBM4 家族成型

· 6 min read
Industry Research Team

当 MI430X 与第六代 EPYC 确定驱动欧洲 LUMI-AI 超算,AMD 的 HBM4 家族不再只是 PPT 上的参数表,而是正在被国家级算力项目、超大规模云厂商与 AI 实验室同时验证的产品矩阵。本文盘点 MI400 系列的完整版图,以及它背后的收购组合拳。

MI400 系列:一张覆盖三大场景的产品矩阵​

MI400 系列于 CES 2026 正式发布,在 Advancing AI 2026 上确认了清晰的 SKU 分层。三款产品覆盖了数据中心采购的三种典型场景:

型号定位显存算力出货时间
MI455X前沿训练 + 推理旗舰(Helios 机架专用)432GB HBM440 PFLOPS 级 MXFP4(dense)2026 H2 起量产
MI430XHPC / 主权 AI(硬件 FP64 加速)432GB HBM4硬件 FP64 288 TFLOPS2027 H1
MI350P企业存量升级(风冷 PCIe)144GB HBM3E4.6 PFLOPS MXFP4已出货

再往远看,AMD 已在 Advancing AI 2026 预告了下一代 MI500 系列:CDNA 6 架构、台积电 2nm、HBM4E 显存,预计 2027 年发布,由 AMD 与 OpenAI 联合定义开发。从 MI400 到 MI500,加上此前的 MI350(CDNA 4)与 MI300X,AMD 的产品路线第一次形成了以年度为节奏的完整梯队,而非零星的单点反击。

值得注意的是,MI455X 与 MI430X 共享同一套 CDNA 5 加 432GB HBM4 的硬件底座——AI 吞吐优先与 FP64 精度优先通过同一平台的不同调校实现,这大幅摊薄了研发与生态适配成本。

MI430X:用 FP64 锁定国家级超算​

MI430X 是 MI400 家族中最具象征意义的一款。它与 MI455X 同样配备 432GB HBM4、23.3TB/s 带宽,但核心差异在于原生硬件级 FP64 双精度:288 TFLOPS,约为 NVIDIA Vera Rubin 的 8.7 倍。这是一个精准卡位——双精度科学计算是 NVIDIA 在消费级 AI 浪潮中相对弱化的领域,而它恰恰是国家级超算的刚需。

MI430X 已经锁定两套国家级系统:

  • 美国 ORNL "Discovery":橡树岭国家实验室新一代超算,2028 年部署;
  • 法国 "Alice Recoque":GENCI 与 CEA 联合打造的欧洲系统。

AMD 官方已在 8 月 4 日财报电话会确认,MI430X 正在 ORNL 与法国 Jean Zay 的 exascale 级超算中运行。而根据最新进展,MI430X 与第六代 EPYC 将共同驱动欧洲 LUMI-AI 超算——LUMI 是欧洲最强的超算系统之一,其 GPU 分区此前基于 MI250X,此次升级至 HBM4 平台,是欧洲主权 AI 对 AMD 路线的直接背书。

超算背书对 ROCm 生态的拉动​

国家级超算项目的价值远超订单本身。超算是软件生态最好的试炼场:混合精度科学计算、大规模 MPI 并行、异构调度,这些极端场景会把 ROCm 的短板逼出来并倒逼修复。同时,超算项目通常要求开源软件栈与长期维护承诺,这与 ROCm 的开源路线天然契合。ORNL、Jean Zay、Alice Recoque、LUMI-AI 构成的"超算联盟",正在为 ROCm 提供一种商业市场买不到的信誉资产——当欧洲与美国的公共算力项目都选择 AMD 时,商业客户的采购顾虑会显著降低。

平台协同:EPYC Venice 与 2nm 双线量产​

MI400 家族的算力释放离不开主机侧的配套。第六代 EPYC "Venice"(Zen 6,最高 256 核,1.6TB/s 内存带宽)已在台积电 2nm 产线启动量产,并延伸至美国亚利桑那工厂——这使 AMD 成为唯一在两个地区都有先进制程量产能力的 x86 服务器 CPU 厂商。下一代 "Verano" 已为 AI 工作负载预留设计,将延续 CPU 与 GPU 平台协同的打法。

CPU 与 GPU 的协同不是简单的搭配销售。在 Helios 机架中,每托盘 4 颗 MI455X 配 1 颗 Venice,CPU 负责数据搬运与调度,CPU-GPU 互联带宽是上一代的 2 倍。对推理集群而言,主机侧的数据预处理好坏直接影响 GPU 利用率——这正是 AMD"CPU 加 GPU 双引擎"路线在 AI 时代的复利。

收购组合拳:内存、推理与空间智能​

围绕 MI400 平台,AMD 在 2026 年展开了一组方向明确的收购:

收购标的能力方向战略意图
MEXT内存访问优化强化 HBM4 时代的显存子系统效率
Taalas快速推理硬件补充推理专用架构能力
World Labs空间智能 / 物理 AI卡位世界模型与机器人时代

三笔收购分别对应内存、推理与物理 AI 三条线,加上与 OpenAI、Meta 各约 1000 亿美元级的合作以及 Anthropic、微软的合作,AMD 正在从"卖芯片"走向"卖 AI 基础设施能力"。这组拼图的完整解读,我们将在后续文章中展开。

市场机会与追赶空间​

AMD 管理层看到的机会窗口清晰而巨大:推理与数据中心 CPU 合计 2200 亿美元的市场机会。推理是 AI 商业化落地的主战场——训练市场已被 NVIDIA 牢固占据,但推理市场的格局远未定型,对显存容量、单位 token 成本与开放生态的敏感度更高,这正是 MI400 家族的差异化所在。

但差距同样不能回避:AMD 的市值仍不足 NVIDIA 的五分之一,CUDA 生态的迁移成本依然存在。分析师普遍认为,这种差距本身就是追赶空间——如果 MI400 系列与 Helios 的 6GW 级订单按期兑现,AMD 在 AI 加速器市场的份额将获得结构性提升。

小结​

MI400 系列的意义在于"家族成型":MI455X 打前沿训练与推理,MI430X 用 FP64 锁定 HPC 与主权 AI,MI350P 覆盖企业存量升级,MI500 预告下一代——四个层次共享平台底座,配合 EPYC Venice 的 2nm 双厂量产,AMD 第一次拿出了一条完整、连贯、可预期的数据中心产品线。LUMI-AI 等超算的背书正在为 ROCm 生态积累信誉,而 MEXT、Taalas、World Labs 的收购则为这张版图补上了内存与物理 AI 的拼图。2027 年 MI430X 正式出货时,我们将能看到这套组合拳的完整威力。

HBM4 Mass-Production Year One: Samsung Yield Breaks 80%, Three Giants Pass NVIDIA Certification, the Last Bottleneck of AI Compute Supply

· 6 min read
Industry Research Team

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.


1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

TimelineSamsung HBM4 YieldNotes
Feb 2026 (mass production start)Under 60%Line ramp-up period
Early Aug 2026~80%Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.


2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor2026 Rubin HBM4 Allocation (est.)Notes
SK Hynix60%–70%Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung25%–30%Rapid share gains after yield leap
MicronRemainderLimited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.


3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

  • Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
  • HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
  • Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

SpecHBM4 (12-Hi / 16-Hi)HBM4E
Per-stack capacity36 GB / 48 GB—
Pin rate11.7–13.0 Gbps16 Gbps
Per-stack bandwidthup to 3.3 TB/sup to 3.6 TB/s
Bus width2048-bit—
Energy efficiency+40% vs HBM3E—
Thermal resistance / cooling+10% improvement / +30%—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.


5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

  • 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
  • The industry already anticipates significant price increases;
  • For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.


6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

References​


This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

AMD MI455X Stuns at CES 2026: AI Chip Performance Up 1000x in 4 Years

· 6 min read
Industry Research Team

On January 5, 2026, on the opening day of CES 2026 (Consumer Electronics Show), AMD Chair and CEO Dr. Lisa Su unveiled in her keynote: the Instinct MI400 series AI accelerators.

The most eye-catching is MI455X — AMD's most powerful AI accelerator ever, using a 2nm + 3nm hybrid process, 432GB HBM4, with FP4 compute up to 40 PFLOPS (20 PFLOPS FP8).

Key highlights​

  • MI455X: FP4 40 PFLOPS, FP8 20 PFLOPS, 10× over MI355X
  • MI450: cost-performance version, FP4 28 PFLOPS, 288GB HBM4
  • Process upgrade: world's first AI chip with 2nm + 3nm hybrid process (GCD on 2nm, MCD on 3nm)
  • Memory upgrade: from MI350X's 288GB HBM3e to 432GB HBM4 (MI455X)
  • Bandwidth upgrade: from MI350X's 8 TB/s to 19.6 TB/s (2.45×)
  • Architecture upgrade: from CDNA 4 to CDNA 5
  • Mass production: MI455X Q4 2026, MI450 Q3 2026

Full MI400 series specs​

📌 Important correction (2026-06-16): After official spec verification, MI455X memory is 432GB HBM4 (not the earlier reported 288GB), and FP4 compute is 40 PFLOPS. Corrected herein.

ModelPositioningMemoryFP4 computeFP8 computeTDP (est.)
MI455XFlagship training+inference432GB HBM440 PFLOPS20 PFLOPS~1,000W
MI450Cost-performance training288GB HBM428 PFLOPS14 PFLOPS~800W
MI440XEnterprise inference216GB HBM425 PFLOPS12.5 PFLOPS~600W
MI430XHPC / scientific computing192GB HBM420 PFLOPS10 PFLOPS~500W
MI400XGeneral / edge inference128GB HBM412 PFLOPS6 PFLOPS~400W

Key upgrades (vs MI350 series):

  • Memory: HBM3e → HBM4, capacity +50% (432GB vs 288GB)
  • Bandwidth: 19.6 TB/s (vs MI350's 8 TB/s, +2.45×)
  • Compute: FP4 40 PFLOPS (vs MI355X's 20 PFLOPS, +2×)
  • Process: 2nm + 3nm hybrid (GCD on 2nm, MCD on 3nm)
  • Architecture: CDNA 5 (vs MI350's CDNA 4)

Performance vs. MI355X​

MetricMI355X (2025)MI455X (2026)Improvement
FP4 compute20 PFLOPS40 PFLOPS2×
FP8 compute10 PFLOPS20 PFLOPS2×
Memory capacity288GB HBM3e432GB HBM41.5×
Memory bandwidth8 TB/s19.6 TB/s2.45×
ProcessTSMC 3nm2nm + 3nm hybridNew gen
ArchitectureCDNA 4CDNA 5New gen
TDP800-1000W~1,000WFlat

Lisa Su at CES 2026:

"Four years ago, MI250's AI performance was X. Today, MI455X's performance is 1000× that. That's the pace of AI chip progress."

CDNA 5 architecture in detail​

The MI400 series adopts the CDNA 5 architecture (MI355X uses CDNA 4):

Key upgrades​

  1. Matrix Core upgrade: FP8/INT8/FP16 support, sparsity acceleration
  2. HBM4 controller: 12-layer HBM4 (vs HBM3e's 8 layers)
  3. Infinity Fabric 4.0: 50% higher die-to-die / die-to-GPU bandwidth
  4. Native sparsity support: MoE Expert-Parallel optimization
  5. Long-context optimization: 1M+ token KV Cache acceleration

vs. NVIDIA Blackwell / Rubin​

MetricAMD MI455XNVIDIA B200NVIDIA Rubin R200 (2026 Q4)
FP4 compute40 PFLOPS20 PFLOPS (45 sparse)~40 PFLOPS (est.)
FP8 compute20 PFLOPS10 PFLOPS (22.5 sparse)~20 PFLOPS (est.)
Memory432GB HBM4192GB HBM3e288GB HBM4
Memory bandwidth19.6 TB/s8 TB/s13 TB/s
TDP~1,000W700-1000W~1,000W
Process2nm + 3nm hybridTSMC 4npTSMC 3nm
Mass production2026 Q42024 Q42026 Q4
Software ecosystemROCmCUDACUDA
StrengthMemory capacity, open ecosystemMost mature ecosystemNext-gen architecture
WeaknessSoftware ecosystem gapSmaller memoryNot yet launched

Conclusion: MI455X leads B200 in FP4/FP8 compute and memory capacity/bandwidth, but software ecosystem remains a weak point. Versus Rubin R200, paper specs are close, but Rubin has the CUDA ecosystem moat.

Production timeline​

TimeEvent
June 12, 2025MI400 series specs first announced at Advancing AI
January 5, 2026MI455X/MI450/MI440X formally launched at CES 2026
2026 Q3MI450 sampling begins
2026 Q4MI455X mass production
2026 Q4MI440X (enterprise inference) launched
2027 Q1MI430X/MI400X (HPC/edge inference) launched
2027MI500 series (next gen)

AMD AI chip roadmap (2025-2027)​

TimeProductProcessNotes
Q4 2024MI325XTSMC 5nmHBM3e upgraded
Q3 2025MI355X (MI350 series)TSMC 3nmCDNA 4, 288GB HBM3e
Q4 2026MI455X (MI400 series)2nm + 3nm hybridCDNA 5, 432GB HBM4
Q1 2027MI500 seriesTSMC 2nm (est.)Next gen, further gains

Software ecosystem: ROCm's progress and challenges​

✅ Progress​

  • PyTorch 2.5+: native MI300X/MI455X support
  • Hugging Face Transformers: official AMD GPU support
  • vLLM 0.8+: MI300X inference support (experimental)
  • JAX: AMD adapting (vs Google TPU)

⚠️ Challenges​

  • Framework optimization: PyTorch on AMD GPUs still below NVIDIA
  • Operator coverage: some niche operators need hand-written HIP
  • Multi-card communication: RCCL (vs NCCL) still lags
  • Developer ecosystem: tutorials, cases, community activity far below NVIDIA

Competitive comparison​

VendorProductFP4 computeMemoryMass productionStrengthWeakness
AMDMI455X40 PFLOPS432GB HBM42026 Q4Largest memory, open ecosystemSoftware gap
NVIDIAB20020 PFLOPS192GB HBM3e2024 Q4Most mature ecosystemSmaller memory
NVIDIARubin R200~40 PFLOPS288GB HBM42026 Q4Next-gen architecture, CUDAExpensive
HuaweiAscend 910C~1.6 PFLOPS64GB HBM2026 Q2China-localizedExport-controlled
GoogleTPU 8t~9.2 PFLOPS~256GB HBM3eLate 2027Gemini-integratedGoogle Cloud only

Industry impact​

1. Impact on NVIDIA​

On paper, AMD MI455X has already caught up to B200 (FP4 40 PFLOPS vs 20 PFLOPS), even leading substantially in memory capacity (432GB vs 192GB).

But:

  • NVIDIA has the CUDA ecosystem moat
  • NVIDIA has the Vera Rubin platform (full solution, 2026 Q4)
  • AMD only sells cards/nodes, NVIDIA sells AI factories
  • MI455X mass production (2026 Q4) coincides with Rubin R200 — head-on competition

2. Pressure on domestic chips​

MI455X's launch means: mainstream international AI chips enter the 2nm + HBM4 era in 2026.

Domestic chips (Huawei Ascend, Cambricon, MetaX, etc.) need to:

  • Catch up to 5nm + HBM3e by 2026-2027
  • Otherwise the gap widens from "1 generation" to "2 generations"

3. Significance for cloud providers​

MI455X gives cloud providers a second option beyond NVIDIA:

  • Microsoft Azure: already deployed MI355X, may follow with MI455X
  • Google Cloud: in-house TPU, won't use AMD
  • Amazon AWS: in-house Trainium/Inferentia, won't use AMD
  • Alibaba Cloud, Tencent Cloud: may procure MI455X as NVIDIA alternative

References​


This article is compiled from AMD CES 2026 official announcements, Baidu Baike, and Zhihu on-site reports; specs verified against official sources. Updated 2026-06-16: corrected MI455X memory (288GB → 432GB) and compute (FP8 6 PFLOPS → FP4 40 PFLOPS).