5 posts tagged with "OpenAI"

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

August 23-25, 2026, the 38th Hot Chips (HC38) was held at Stanford's Memorial Auditorium. As the bellwether of global high-performance chip architecture, this conference landed exactly at the most intense moment of the AI compute arms race — the official agenda had 48 entries, including 7 AI accelerators, 6 memory tutorials, 6 CPUs, and 4 each of GPUs and networking. Putting the vendor talks together, one consensus emerged: the unit of AI compute competition has shifted from "single chip" to "whole rack / entire system."

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1. Overview: Three Days of Agenda, Almost a Preview of the 2027 AI Rack Market​

Monday (8/24) afternoon's GPU session was the focus, with four talks nearly colliding as the 2027 AI rack market:

• NVIDIA Rubin GPU ("Driving the Era of Agentic AI"): First chiplet-architecture GPU, 288GB HBM4, ~50 PFLOPS FP4, paired with 88-core Arm-architecture Vera CPU into NVL72 / NVL144 racks, mass production in H2 2026.
• AMD Instinct MI400 (two talks: architecture + system architecture): Told the "rack-scale" story thoroughly.
• Intel Crescent Island: A 350W air-cooled card designed for Agentic AI inference.

Tuesday (8/25) afternoon's AI session was almost a parade of "hyperscalers de-NVIDIA-izing": Google's 8th-gen TPU, OpenAI's first custom chip, Microsoft Maia 200, Meta MTIA, and Cerebras wafer-scale rack all appeared together.

Every vendor on stage used the term "Agentic AI" within the first two PPT slides — not a coincidence, but the collective shift in 2026 AI workload design goals.

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2. NVIDIA Rubin: One Rack Is a Supercomputer​

What NVIDIA featured at Hot Chips was not a single GPU but the Vera Rubin NVL72 whole cabinet — 72 Rubin GPUs + 36 Vera CPUs, 18 compute trays + 9 NVLink switch trays, about 1.3 million components, nearly 1,300 chips, weighing about 4,000 pounds (~1.8 tons).

The single Rubin GPU specs are equally stunning:

Metric	Rubin GPU	vs Blackwell
Transistors	336 billion (TSMC 3nm dual-die)	208 billion (+61.5%)
Memory	288GB HBM4	—
Bandwidth	22 TB/s	2.8× Blackwell
NVFP4 inference	50 PFLOPS	5× GB200
Training compute	35 PFLOPS	3.5×

The most disruptive design is in the compute tray: no cables, no hoses, no fans, all interconnected via the PCB backplane. NVIDIA says assembly time dropped from nearly 2 hours to 5 minutes (20× faster) while improving maintainability.

This time NVIDIA is selling not FLOPS but tokens per megawatt. Citing a SemiAnalysis benchmark based on DeepSeek-v4-PRO (140K+ context, AgentX workload), it claims: versus GB300 NVL72, Vera Rubin NVL72 delivers 10× to up to 30× tokens/MW as interaction intensity rises. A single cabinet provides 3.6 EFLOPS inference compute, whole-cabinet power 190-230kW; long-term capacity target is 1,000 NVL72 cabinets per day.

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3. AMD MI455X + Helios: Bigger Memory and Open Interconnect​

AMD's answer is the MI455X + Helios rack going head-to-head with NVIDIA. MI455X uses CDNA 5 architecture, 8 N2-process accelerator dies + N3P-process interconnect die, 256 workgroup processors, 192MB global L2.

Metric	MI455X	vs Rubin
Memory	432GB HBM4 (12-layer stack)	50% higher than Rubin's 288GB
Bandwidth	23.3 TB/s	Slightly ahead
MXFP4 compute	40.26 PFLOPS	—
System (Helios 72 cards)	2.9 ExaFLOPS FP4 inference	—
Price	~$5.25M per cabinet	—

At the system level, AMD bets on the UALoE (Ultra Accelerator Link over Ethernet) open standard: each GPU provides 3.6 TB/s bidirectional interconnect bandwidth; two 512-port 200G UALoE switch chips in the switch tray total 10.8 TB/s — opening the interconnect protocol to the whole industry while targeting NVLink.

Production cadence: AMD plans to deliver engineering samples and small-batch systems in H2 2026, with large-scale ramp in Q2 2027. Earlier rumors of Helios delay due to cooling issues were not confirmed by AMD.

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4. Intel Crescent Island: The Air-Cooled, Large-Memory "Cost-Effective Oddball"​

Intel offers a completely different path: Crescent Island — a 350W, air-cooled, standard-PCIe-slot inference GPU designed for Agentic AI, with the key metric being tokens per watt.

Metric	Crescent Island	Note
Architecture	Xe3P, 32 Xe cores, 32MB unified L2	Disclosed at Hot Chips
Memory	Intel branded card 160GB / ODM up to 480GB LPDDR5X	More than Rubin's 288GB HBM4
Form factor	350W air-cooled PCIe	Plugs into standard racks, no liquid-cooling retrofit
RAS	ECC, dynamic page offline, hard-package repair, PCIe advanced error reporting	Addresses "silent data corruption"

Intel's logic is clear: inference scenarios need far more memory capacity than bandwidth; using low-cost LPDDR5X for capacity and air cooling to skip liquid-cooling infrastructure drives down per-token cost. Combined with Diamond Rapids Xeon (256 performance cores, 1.28GB cache, 128 PCIe Gen6 lanes), Intel tries to surround from edge to datacenter with "CPU + inference GPU + open software stack."

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5. Custom ASIC Parade: Google, OpenAI, Microsoft, Meta Together​

Tuesday afternoon's AI session was the most historic of the conference — a parade of "hyperscalers de-NVIDIA-izing":

Chip	Vendor / Partner	Positioning	Key Specs / Progress
TPU 8t (Sunfish)	Google × Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM
TPU 8i (Zebrafish)	Google × MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prev gen), ICI 19.2 Tb/s
Jalapeño	OpenAI × Broadcom	Inference	9-month end-to-end design, target ~50% token cost cut, commercial end of 2026
Maia 200	Microsoft (TSMC 3nm)	Inference	140B+ transistors, 10+ PFLOPS FP4, 216GB HBM3E, serving GPT-5.2 at Des Moines datacenter
MTIA 300-500	Meta (RISC-V) × Broadcom	Training + inference	Up to 25× compute gain, one model every 6 months before 2027

Google split TPU into training (8t) and inference (8i) dedicated architectures for the first time — its biggest architectural shift in a decade. Norm Jouppi personally took the stage to present TPU v8.

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6. Two Hidden Threads — Memory and Networking: HBM4 Year 1 + AI Factory OS​

Beyond GPUs/ASICs, two hidden threads mattered equally:

• Memory: Samsung's HBM Base Die (logic-process base die) and SK hynix's advanced packaging appeared together; the HBM4-era "base-die foundry" industry shift begins; HBF (high-bandwidth flash), LPDDR5X-PIM, 3D DRAM, and CXL compute-storage showcased "compute-in-memory" moving from papers to products.
• Networking: NVIDIA BlueField-4 (DPU) and Spectrum-X Multiplane architecture (presented by Gilad Shainer) — networking is becoming the decisive architecture for gigascale AI, scaling from hundreds of thousands to a million cards; Broadcom Thor Ultra Ethernet NIC keeps pressing; Mojo Vision showed chip-level optical I/O.

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7. Three Routes, One Consensus​

At the same conference, three vendors offered three distinctly different AI compute delivery philosophies:

1. NVIDIA: Full-stack closed integration — GPU, CPU, DPU, and switch chips all self-designed, pushing system performance to the extreme via ultimate software-hardware co-design, at the cost of deep customer lock-in.
2. AMD: Open-standard catch-up — Uses larger HBM4 capacity + UALoE open interconnect for a "cost-effective + open" play, tearing open the inference gap with Meta and OpenAI's 12GW-class orders.
3. Intel: Air-cooled cost-effectiveness — Abandons liquid cooling and HBM, uses LPDDR5X large memory + standard PCIe, betting that "most inference doesn't need a 200kW rack."

But all three agree: the unit of competition is no longer the chip, but the co-designed system (rack / system). For buyers, 2027 compute planning should compare not "single-card PFLOPS" but "tokens per megawatt, latency, availability, and full-lifecycle cost."

Related Links​

• NVIDIA Rubin spec page
• AMD MI455X spec page
• Intel Crescent Island spec page
• Google TPU 8t spec page
• Google TPU 8i spec page

References​

• Hot Chips 2026 Three Giants Together: Rubin 336B Transistors, MI455X 432GB, Crescent Island 480GB - IC Chip Industry Watch
• Hot Chips Day 2: Rubin, MI400 and Diamond Rapids Go Head-to-Head - AI2Work
• NVIDIA Vera Rubin NVL72 Rack at Hot Chips 2026 - ServeTheHome
• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim

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This article is compiled from Hot Chips 2026 (Aug 23-25) official presentations and on-site reports from ServeTheHome, SemiAnalysis, TechPowerUp, etc. Performance data are vendor-disclosed figures; actual performance subject to mass-produced products.

The Tuesday-afternoon AI session at Hot Chips 2026 this August was the most historically significant of the conference — not because any single chip was so powerful, but because almost everything on stage was a "hyperscaler de-NVIDIA-ization" custom ASIC: Google's 8th-gen TPU, OpenAI's first self-designed chip, Microsoft Maia, Meta MTIA, and Cerebras wafer-scale racks, all on one stage. When the world's largest AI compute buyers start treating GPUs as "one of the options," the power structure of AI hardware is loosening.

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1. OpenAI Jalapeno: Building a Chip in 9 Months​

On June 24, 2026, OpenAI, together with Broadcom, unveiled its first self-designed inference ASIC, Jalapeno — the fifth member of the "custom inference chip club."

Dimension	Jalapeno
Partner	Broadcom + TSMC manufacturing
Positioning	Inference-specific ASIC
Design cycle	9 months end-to-end (Greg Brockman says aided by OpenAI's own models)
Cost target	~50% lower token cost vs general-purpose GPU stack
Commercial timing	First deployments by end-2026; long-term goal 10GW of self-designed chips
Deal scale	Up to $10B strategic partnership with Broadcom (accelerators + networking by 2029)

The talk title "You Can Just Build Things … Chips" is itself a signal: the largest AI compute buyer no longer defaults to GPU as the only path.

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2. Google TPU v8: The Biggest Architectural Pivot in a Decade — Train/Infer Split​

Google has the longest custom-chip history (2016 to now), and its 8th-gen TPU for the first time splits the product line in two:

Model	Codename	Partner	Positioning	Key Specs
TPU 8t	Sunfish	Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM, 2× ICI bandwidth
TPU 8i	Zebrafish	MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prior gen), 19.2 Tb/s ICI

On capacity, Morgan Stanley estimates based on supply-chain interviews that Google TPU production in 2026 may exceed 3 million units (a brokerage estimate, not an official target). Google is also the only vendor to achieve large-scale custom-chip deployment and sell compute externally (Gemini runs on TPUs).

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3. Meta MTIA: From Recommendation Systems to a GenAI Dual Mission​

Meta's custom journey has the clearest starting point — MTIA was originally built for recommendation ranking hardware and is being pulled toward a dual mission by generative AI.

• MTIA 300 is deployed; 400 / 450 / 500 are planned at roughly one new model every 6 months through 2027;
• Based on RISC-V, Meta claims up to 25× compute gain;
• Node evolves with industry cadence: 100 (7nm) → 200 (5nm) → 300 series (3nm + CoWoS);
• In partnership with Broadcom; another chip codenamed Iris reportedly passed testing in July 2026;
• Meta plans to start volume production of one of them in September 2026, doubling its overall compute.

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4. Microsoft Maia 200/300: Most Advanced Deployment​

Microsoft's Maia 200, released January 26, 2026, is the most advanced in deployment among the four:

Dimension	Maia 200
Process	TSMC 3nm, 140B+ transistors
Compute	10+ PFLOPS FP4 / 5 PFLOPS FP8
Memory	216GB HBM3E, 7 TB/s
Power	750W
Deployment	Already running in Des Moines data center, serving OpenAI GPT-5.2 and Microsoft 365 Copilot

Microsoft claims roughly 3× the performance of Amazon's Trainium on specific benchmarks. The short-term strategy is a dual track of "self-designed Maia + purchased NVIDIA" in parallel — self-designed chips need time from design to mass production, and NVIDIA's mature ecosystem cannot be replaced in the short term.

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5. Amazon Trainium 3 and Anthropic's In-House Team​

• Amazon: The Trainium series is already commercial, with 1.4 million units cumulatively deployed (officially disclosed) — a multi-billion-dollar business; its strength is the AWS customer base, letting enterprises choose between NVIDIA GPUs and self-designed chips. Trainium 3 continues this path.
• Anthropic: In August 2026 announced the formation of an in-house chip team, with no tape-out or mass-production timeline yet; initially positioned as a complement (not a replacement) to existing partnerships with NVIDIA/AMD/AWS/Google Cloud, aiming to tailor-build for the Claude architecture and shed reliance on a single GPU.

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6. NVIDIA's Answer: Not a Faster GPU, But Full-Stack​

It's easy to simplify the narrative to "four companies build chips, NVIDIA defends GPU." But NVIDIA took 6 slots at Hot Chips: a RISC-V tutorial, the Vera CPU, the Rubin GPU, the BlueField-4 DPU, the Spectrum-X multi-plane network, and an LPU accelerator.

A hyperscaler ASIC replaces only one of those five pillars. If the CPU, NIC, switching fabric, and software all come from the same vendor, what you save by swapping out the accelerator is far less than the accelerator line item on the bill suggests. Rubin's play is a full-stack AI factory platform spanning seven chips and five racks — the competitive answer is "full-stack positioning," not "a faster single chip."

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7. Trend Judgment: Inference De-GPU-izes, Training Still GPU-Led​

• Inference side: The CUDA moat visibly shallows. Inference is parallelizable and replaceable at the endpoint; custom ASICs trade away the generality tax (implementing only the operations LLMs actually execute) for lower cost/token. Groq LPU, Cerebras, and various TPU/ASIC players all compete on the same metric.
• Training side: Foundation models are still trained on GPUs, with no serious challenger in the short term. NVIDIA's three training moats (fastest silicon + NVLink + CUDA) remain firm.
• Conclusion: Custom chips are not "replacing NVIDIA," but giving buyers a credible external negotiation option in the largest and fastest-growing battlefield — inference. That alone is enough to reshape the economics of AI infrastructure.

Related Links​

• Inference Accelerator Market 2026
• Hot Chips 2026 Full Recap
• Google TPU 8t Spec Page
• Google TPU 8i Spec Page

References​

• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim
• Custom AI inference silicon: why OpenAI built Jalapeno - nexi.fund
• Anthropic Builds Custom AI Chips for Claude - Studio Global AI
• 所有大厂都在做同一件事：自己造芯片，少买英伟达的 - Toutiao

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This article is compiled from August 2026 Hot Chips on-site reports, corporate announcements, and industry analysis. Some capacity and performance figures are brokerage estimates or vendor-disclosed figures; actual results are subject to mass-produced products.

June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

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2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

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3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

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4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

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5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

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Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

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Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

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References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

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This article is continuously updated. Please provide the latest developments.

On June 24, 2026, OpenAI and Broadcom jointly announced their first in-house AI inference chip, Jalapeño. This ASIC designed specifically for large language model inference went from design to tape-out in just 9 months and cuts inference cost by roughly 50%, marking OpenAI's transformation from a pure model company into a full-stack AI infrastructure provider.

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1. Core conclusions (read this first)​

Dimension	Jalapeño	Current GPU solution	Advantage
Inference cost	-50%	Baseline	✅ Half the cost
Performance per watt	Clearly superior	Most advanced accelerator	✅ Energy-efficiency lead
Design cycle	9 months	~18 months	✅ 2× faster
Positioning	Inference ASIC	Train+inference GPU	Dedicated optimization
Supply	Internal only	Market purchase	⚠️ Not for sale

One-line summary: Jalapeño is a key step in OpenAI's full-stack AI strategy, using in-house silicon to cut inference cost 50% while opening a new paradigm of "AI-assisted design of AI chips."

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2. What is Jalapeño?​

2.1 Basic information​

Item	Detail
Name	Jalapeño (a chili pepper)
Type	Application-specific integrated circuit (ASIC)
Positioning	Large language model inference
Announced	2026-06-24
Taped out	Sep 2025 (est., 9-month rapid tape-out)
Deployment	End of 2026 (gigawatt-scale data centers)
Partners	Broadcom, TSMC, Celestica
Process	TSMC 3nm
Architecture	Systolic Array
HBM	8 stacks (est. HBM3E or HBM4)

2.2 Why "Jalapeño"?​

Jalapeño is a Mexican chili known for "medium heat, strong flavor." OpenAI's naming hints that the chip:

• ✅ Medium heat: not the most aggressive architecture (vs Cerebras WSE), but effective enough
• ✅ Strong flavor: strong presence in inference scenarios (50% cost reduction)
• ✅ Appetizer: just "the first step of a multi-generation roadmap" (Broadcom CEO Hock Tan)

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3. Deep technical analysis​

3.1 9-month rapid tape-out: the new paradigm of AI-assisted chip design​

Normally, designing an ASIC from scratch takes 1.5 to 2 years. Jalapeño went from initial design to manufacturing tape-out in just 9 months.

Key reason: deep software-hardware co-development

Technique	Description
AI-assisted architecture exploration	OpenAI used its own frontier models (GPT-5.3-Codex-Spark) to explore chip architecture design space
AI power simulation	AI models for power simulation and optimization
RL optimization	RL to optimize chip placement and routing
Broadcom silicon implementation	Broadcom provides top-tier ASIC implementation (network, switch chip experience)

OpenAI President Greg Brockman said:

"We use the frontier models that serve our users to optimize the infrastructure that runs the models of the future."

3.2 Architecture optimized for inference​

Unlike general-purpose GPUs, Jalapeño is an ASIC built from scratch around OpenAI's deep understanding of LLM inference workloads:

Architecture feature	Description
Reduce data movement	Core principle is minimizing data movement (the main bottleneck in inference)
Balanced compute-memory-network	Resource allocation optimized for inference, bringing real utilization closer to theoretical peak
High throughput + low latency	Aims to combine the throughput of leading accelerators with the low latency of the fastest dedicated inference systems
Future model support	Supports not only current models (GPT-5, GPT-5.3) but adapts to next-gen inference needs

3.3 Full-stack platform: more than a chip​

Jalapeño is a multi-generation compute platform, not just a chip:

Component	Supplier	Description
Accelerator chip	OpenAI design, TSMC fab	TSMC 3nm, 8-stack HBM
Network switch chip	Broadcom Tomahawk	High-speed interconnect (competes with NVIDIA NVLink)
Board, rack, system	Celestica	Full-rack solution
Software stack	OpenAI	Deep adaptation for GPT, Codex, Agent products

Deployment target: gigawatt-scale data centers

Broadcom CEO Hock Tan said:

"Jalapeño will begin deployment this year in gigawatt-scale data centers with Microsoft and other partners."

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4. Performance and cost analysis​

4.1 Inference cost cut 50%​

Although OpenAI's official release was conservative on Jalapeño's cost savings — only stating its "performance per watt is substantially better than today's state of the art" without a specific percentage — per Bloomberg, Broadcom CEO Hock Tan revealed:

Early internal tests show Jalapeño achieves roughly 50% inference cost savings versus today's mainstream AI GPUs.

Significance for OpenAI:

Item	Current (GPU)	Jalapeño	Savings
Daily API calls	Hundreds of millions	Hundreds of millions	—
Inference cost share	~60-70% of operating cost	~30-35%	-50%
Annual compute spend	Billions of dollars	Hundreds of millions	Saves billions

4.2 Performance per watt clearly better than state of the art​

OpenAI's announcement states:

"Jalapeño engineering samples have successfully run complex reinforcement-learning tasks such as GPT-5.3-Codex-Spark at target frequency and power; early tests show performance per watt substantially better than today's most advanced AI accelerators."

Comparison target: NVIDIA Blackwell (today's most advanced AI accelerator)

Metric	Jalapeño	NVIDIA Blackwell	Note
Performance per watt	Clearly superior	Baseline	OpenAI official statement
Inference latency	On par with fastest dedicated inference systems	Baseline	Target
Throughput	On par with leading accelerators	Baseline	Target
TDP	Not disclosed (est. 400-700W)	700-1000W	Jalapeño possibly lower

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5. Impact on the AI chip market​

5.1 "De-NVIDIA-ification" accelerates​

Jalapeño's launch is another footnote in big-tech's collective challenge to NVIDIA's market dominance:

Vendor	In-house chip	Type	Status	Relation to OpenAI
Google	TPU v6e / Ironwood	Train+inference	✅ Commercial	Google Cloud supplies OpenAI
Amazon	Trainium 3	Training	✅ Launched	AWS supplies OpenAI
Microsoft	Maia 100	Train+inference	✅ Launched	OpenAI exclusive partner
Meta	MTIA	Train+inference	✅ Launched	—
Apple	Neural Engine	On-device inference	✅ Commercial	—
OpenAI	Jalapeño	Inference	🚧 Deploy end of 2026	Internal + possibly sold to third parties

5.2 OpenAI is not about to fully "abandon" NVIDIA​

Brockman admitted:

"We simply cannot get compute fast enough."

Currently OpenAI is simultaneously procuring chips from NVIDIA, AWS, AMD, and Cerebras; Jalapeño is a structural supplement to its explosive compute demand, not a replacement.

5.3 Possibly sold to third parties​

Broadcom CEO Hock Tan specifically emphasized:

"This is just 'the start of a multi-generation roadmap'; OpenAI and Broadcom aim to jointly build gigawatt-scale compute clusters."

This means OpenAI may sell its hardware to third parties, provided it can secure enough supply from Broadcom and TSMC.

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6. Jalapeño vs other in-house chips​

Metric	Jalapeño (OpenAI)	TPU v6e (Google)	Trainium 3 (Amazon)	Maia 100 (Microsoft)
Announced	2026-06-24	2024	Q4 2025	2023
Type	Inference ASIC	Train+inference TPU	Training ASIC	Train+inference
Process	TSMC 3nm	TSMC 4nm	TSMC 5nm (est.)	TSMC 5nm (est.)
For sale	❌ Internal only (maybe later)	✅ GCP	✅ AWS	❌ Internal only
Design cycle	9 months	~18 months	~18 months	~18 months
AI-assisted design	✅ First	❌ No	❌ No	❌ No
Cost advantage	-50% inference cost	Optimized	Optimized	Optimized

Key differences:

• ✅ Jalapeño is the first AI chip designed with AI assistance
• ✅ Jalapeño design cycle only 9 months (industry average 18 months)
• ⚠️ Jalapeño not for sale (at least for now)

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7. Future roadmap​

7.1 Multi-generation chip platform​

Jalapeño is just "the start of a multi-generation roadmap":

Time	Event
End of 2026	Jalapeño initial deployment (gigawatt-scale data centers)
2027	Jalapeño v2 (est., architecture optimization)
2027-2028	Jalapeño training version (est., challenging TPU/Trainium)
2028 and beyond	Gigawatt-scale compute cluster fully built

7.2 OpenAI full-stack AI infrastructure strategy​

Layer	OpenAI in-house	Outsourced/procured
Models	✅ GPT-5, GPT-5.3, Codex	—
Chips	✅ Jalapeño (inference)	NVIDIA GPU, AWS Trainium, AMD GPU
Systems	✅ With Celestica	Microsoft Azure data centers
Network	✅ Broadcom Tomahawk	Microsoft Azure network
Cloud platform	❌ None	Microsoft Azure (exclusive partner)

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8. Industry reaction and expert views​

8.1 Supportive views​

Expert	View
Broadcom CEO Hock Tan	"Jalapeño is just the start of a multi-generation roadmap; the goal is to jointly build gigawatt-scale compute clusters."
OpenAI President Greg Brockman	"We use the frontier models that serve our users to optimize the infrastructure that runs the models of the future."
Industry insiders	"Jalapeño's launch is another footnote in big-tech's collective challenge to NVIDIA's market dominance."

8.2 Skeptical views​

Concern	Description
Not for sale	Currently internal only; third parties cannot purchase, limited impact on NVIDIA's market share
Software ecosystem	OpenAI must build its own software stack; competing with CUDA is hard
Supply capacity	TSMC capacity is limited; can it meet OpenAI + Broadcom + other customers' demand?
Opaque performance data	OpenAI has not released specs (compute, memory, bandwidth, TDP), hard to assess objectively

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9. Significance for developers​

9.1 If OpenAI sells Jalapeño to developers in the future...​

Scenario	Current (NVIDIA GPU)	Future (Jalapeño)
Inference cost	Baseline	-50%
Inference latency	Baseline	Possibly lower
Software stack	CUDA + TensorRT	OpenAI API (possibly open-source stack)
Procurement difficulty	High (export controls, supply shortage)	Low (OpenAI direct supply)

9.2 Worth watching even if not sold​

• ✅ 50% inference cost cut forces NVIDIA, AMD, Intel to lower GPU prices
• ✅ The AI-assisted chip design paradigm will be rapidly copied by the industry
• ✅ The 9-month tape-out cycle becomes a new industry benchmark

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10. Summary​

Dimension	Assessment
Technology innovation	⭐⭐⭐⭐⭐ First AI chip designed with AI assistance, 9-month tape-out
Cost advantage	⭐⭐⭐⭐⭐ 50% inference cost cut, billions saved annually
Strategic significance	⭐⭐⭐⭐⭐ OpenAI transforms from pure model company to full-stack AI infrastructure provider
Market impact	⭐⭐⭐⭐ "De-NVIDIA-ification" accelerates, big-tech in-house chip camp grows
Openness	⭐⭐ Internal only for now, possibly sold to third parties later

Final recommendations:

• 🇨🇳 China market: Keep watching Huawei Ascend, Cambricon MLU, Moore Threads MTT (Jalapeño not sold to China)
• 🌍 International market: Watch whether Jalapeño is eventually sold externally and its impact on NVIDIA's market share
• 💡 Developers: Watch for possible OpenAI API price cuts (50% inference cost cut may partially pass through)

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References​

• OpenAI official announcement (technical white paper pending)
• Broadcom CEO Hock Tan interview
• Bloomberg: Jalapeño inference cost cut 50%
• SemiWiki: Jalapeño technical details
• Tom's Hardware: Jalapeño architecture analysis
• ESMChina: Jalapeño 9-month tape-out

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Disclaimer: Some specs in this article are estimates, subject to OpenAI's official technical white paper. OpenAI will release a detailed performance white paper in the coming months.

Last updated: June 26, 2026