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18 posts tagged with "Roadmap"

Vendor AI chip roadmap updates and forecasts

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xAI 与特斯拉 Dojo 2:非典型玩家的自研芯片路线

· 4 min read
Industry Research Team

在超大规模云厂商与芯片大厂之外,马斯克的两家公司给出了自研芯片的另一种打开方式:一家砍掉自研训练超算、押注推理芯片量产,一家干脆不造芯片、把租来的 GPU 堆成全球最大集群。

Dojo 的终结与 AI5 的转向​

2025 年 8 月,马斯克在社交平台确认解散特斯拉 Dojo 训练超算团队,并给出一句著名判断:Dojo 2 是一条"演化死胡同"。他解释称,当所有路径都汇聚到 AI6 芯片时,特斯拉没有理由同时维持两套差异巨大的芯片设计。这座投入了 5 亿美元的布法罗 Dojo 设施随之失去原有使命。

转向的落点是车载推理芯片。据公开信息,AI5 芯片于 2026 年 4 月完成流片定稿,由台积电亚利桑那厂与三星得州厂双源代工,2027 年年中启动大规模量产,优先服务 Cybercab 与 Optimus 项目;AI6 处于早期开发阶段,目标性能较 AI5 翻倍,定位同时覆盖车载推理、机器人控制与大规模 AI 训练。2026 年 5 月,特斯拉又以 Dojo 2 之名发布了一款面向 Cybercab 的自动驾驶芯片,据业界报道宣称可在 45W 功耗下提供 900 TFLOPS 算力,8 月起批量装车。

阶段关键动作时间线
Dojo 一代D1 芯片加英伟达 GPU 混合集群2023 年上线
项目关停团队解散,D2 芯片搁置2025 年 8 月
AI5台积电与三星双源代工2026 年流片,2027 年中量产
Dojo 2 命名车载推理芯片,45W 下 900 TFLOPS2026 年 5 月发布
AI6目标性能翻倍计划 2028 年量产

"Dojo 3" 的新含义:用通用芯片攒超算​

马斯克为 Dojo 这个名字保留了另一种存续方式:既然 AI5 与 AI6 在推理之外"至少还不错"地能做训练,那么把大量 AI6 芯片集成到单块电路板上,就能构成训练集群,还能把网络布线的复杂度与成本降低几个数量级。他甚至直接表示,"或许可以把它称为 Dojo 3"。这实质上宣告了专用训练芯片路线的终结——用一条高量产的车规芯片产线,摊薄训练集群的芯片成本。

与特斯拉形成有趣对照的是 xAI。这家公司几乎完全放弃了芯片自研,而是以惊人的速度从英伟达采购和租借 GPU,在孟菲斯建成了全球首个吉瓦级训练集群 Colossus 2,并逐步把富余算力对外出租,谷歌、Anthropic 均已成为其大客户。马斯克体系内由此形成分工:xAI 造算力工厂,特斯拉造端侧芯片,训练与推理各取所需。

非典型路线的启示​

特斯拉与 xAI 的组合揭示了自研芯片的另一种经济学:当端侧场景(车辆、机器人)足够确定且出货量足够大时,自研芯片的核心价值在于规模与迭代速度——马斯克甚至希望把未来芯片的设计周期压缩到 9 个月;而当需求爆发快于自研节奏时,直接采购现成 GPU 抢时间,比造芯片更理性。三星与特斯拉之间 165 亿美元的代工协议,也说明车载 AI 芯片已成为先进制程的重要买家。

小结​

Dojo 的落幕并非自研芯片的失败,而是一次清醒的止损:把有限资源从长周期的训练超算转向出货量以百万计的端侧推理芯片。在"要不要自研"这个问题上,马斯克给出了一个与云厂商截然不同却同样自洽的答案——自研与否,取决于你的芯片要装在哪里、装多少颗。

2026年Q4 AI芯片前瞻:Rubin放量、Helios交付、昇腾950DT上市与国产新窗口

· 4 min read
Industry Research Team

2026年进入第四季度,AI芯片竞争的关键词从"发布"转向"交付"。Rubin能否持续放量、Helios能否如期爬坡、昇腾950DT如何定价上市,将共同决定2027年竞争格局的起点。

NVIDIA:Rubin放量与生态开放双线推进​

Q4期间NVIDIA的计划主线:

  • Vera Rubin NVL72:2026下半年持续放量,MLPerf Inference v6.1首秀已登顶(Qwen3-VL较GB300最高3.7倍),HBM4平台优势开始兑现;
  • N1X:基于RTX Spark的PC处理器按计划2026年秋季上市,打开消费级战场;
  • Blackwell Ultra(B300):租用价格参考Nebius口径约9.50美元/GPU小时,仍是当前租赁市场的重要基准;
  • 后续代际:Rubin Ultra等后续路线待发;
  • 生态动作:NVLink Fusion持续开放生态,NVHBM定制内存方案推进。
产品/计划Q4状态
Vera Rubin NVL722026下半年持续放量
N1X秋季上市
B300租用9.50美元/GPU小时(Nebius口径)
Rubin Ultra待发布
NVLink Fusion / NVHBM生态开放与定制内存推进

AMD:Helios从首发出货到Q4爬坡​

AMD在Q4的核心任务是交付:

  • Helios机架:MI455X首批出货目标Q3末,Q4进入量产爬坡阶段;
  • 客户部署:OpenAI 6GW、Meta 6GW部署合作推进中,微软作为首批客户计划2026年下半年交付;
  • MI430X:驱动欧洲LUMI-AI超算,拓展科学计算场景;
  • ROCm:软件生态继续补齐;
  • 下一代:Helios II / MI500级产品路线待公布。

华为:昇腾950DT上市与云服务全球商用​

华为Q4的关键节点最为明确:

  • 昇腾950DT:Q4上市,报价超25万元;
  • 昇腾950智算集群云服务:9月30日已国内商用,11月30日全球商用;
  • 960系列:计划2027年接棒,970/980排在2028-2029年。

阿里平头哥:真武V900量产倒计时​

平头哥的时间表指向2027年:真武V900计划2027年Q1量产上云,配套磐久AL128与50万卡集群规划;J900排期2027年Q3。Q4将进入量产前最后的验证阶段。

OpenAI/博通 Jalapeño:多吉瓦部署推进​

OpenAI与博通合作的Jalapeño定制芯片规格已明确:13.4 PFLOPS(4-bit精度)、232GB内存,多吉瓦部署规划正在推进。这枚自研芯片的量产进度,将直接影响OpenAI未来的算力自给率。

关键变量:三大约束​

Q4的交付兑现程度,将取决于三个外部约束:

  1. HBM供给:戴尔CEO警告2027年可能比2026年更紧缺,HBM产能是所有GPU路线图的共同瓶颈;
  2. 国产涨价传导:昇腾950DT涨价20%-50%、寒武纪690涨价20%-30%(路透,HBM成本驱动),涨价将传导至国产算力服务价格;
  3. 电力约束:Emerald AI/Google/NVIDIA成立的AEMA电网响应模式,预示电力正在成为算力扩张的第一性约束。

三条观察建议​

基于上述事实,给三类角色的观察点(非投资建议):

  • 采购方:昇腾950DT与寒武纪690的涨价幅度表明国产算力已进入卖方市场,锁量谈判宜早不宜迟;同时关注Helios Q4实际爬坡数据,作为第二供应源评估依据;
  • 开发者:ROCm生态补齐与NVLink Fusion开放,意味着2027年异构算力混布的软件门槛正在降低,可提前在推理侧做多框架适配;
  • 投资者:可跟踪的公开观察点包括——Helios首批交付兑现情况、昇腾950云服务11月30日全球商用落地、HBM价格走势对各家毛利率的影响信号。

小结​

2026年Q4是"交付验证季":NVIDIA Rubin放量、AMD Helios爬坡、昇腾950DT上市与云服务全球商用、平头哥V900量产倒计时——各家计划均已排定,剩下的变量集中在HBM供给、涨价传导与电力约束三点。所有时间节点以"计划/预计/排期"口径为准,Q4末回看兑现率,就是对2027年格局的最好预判。

摩尔线程"庐山"GPU年底亮相:3A游戏渲染提升15倍、光追性能提升50倍

· 5 min read
Industry Research Team

从"国产兼容显卡"到"硬件光追+AI生成式渲染",摩尔线程正在完成一次技术范式层面的跃迁——而AI算力与游戏GPU的双线并进,让这次跃迁有了更厚实的商业底座。

"庐山"来了:15倍渲染、50倍光追、64倍AI​

2026年9月3日,摩尔线程在半年度业绩说明会上介绍了下一代高性能图形渲染芯片规划:基于**"花港"架构的新一代GPU——"庐山"**,预计实现三大性能跃升:

  • 3A游戏渲染性能提升15倍
  • 光线追踪性能提升50倍
  • AI性能提升64倍

官方计划于2026年底推出"庐山"芯片(上市时间以官方发布为准)。这三个数字放在一起,勾勒出的不是一次常规的代际迭代,而是一次"重写底座"式的升级:光追50倍意味着硬件光追从"支持"走向"实用",AI性能64倍则预示着AI能力将从图形附庸升级为核心卖点。

两大核心渲染技术​

"庐山"的性能跃升背后,是两项核心渲染技术支撑:

其一是实时光线追踪。"庐山"基于花港架构设计了硬件光线追踪加速引擎,并支持DirectX Raytracing(DXR)。此前国产GPU普遍通过软件手段或有限硬件支持来兼容光追,而专用加速引擎+DXR支持的组合,意味着"庐山"将具备与主流游戏引擎光追管线对接的能力——这是3A游戏生态的门票。

其二是AI生成式渲染AGR。摩尔线程推出全自研的MTAGR 1.0技术,推动渲染范式"从计算走向生成"。传统光栅化渲染是逐像素计算的暴力美学,而生成式渲染借助AI模型直接生成画面细节,用更少的算力换更高的画质与帧率。NVIDIA的DLSS、AMD的FSR已验证了AI超分路径的价值,MTAGR 1.0则是国产GPU在渲染范式变革上的主动跟进——且选择直接押注"生成"而非仅仅"超分"。

双线并进:游戏GPU与AI算力​

"庐山"的故事不止于游戏。摩尔线程2026年的商业化进展呈现出游戏与AI算力两条腿走路的格局:

时间事件意义
此前登陆科创板上市打开资本通道,支撑高研发投入
9月3日半年度业绩说明会公布"庐山"规划图形GPU技术路线图明确
9月19日(报道)京东云与摩尔线程合作万卡级集群部署上线国产GPU万卡集群规模化落地
9月23-27日数贸会(杭州)展示AI智算卡、万卡级集群展示"模型训练工厂/词元生产工厂/智能体生产工厂"

在杭州数贸会上,摩尔线程展示的产品覆盖云-边-端全场景:AI智算卡、万卡级集群,以及面向大模型生命周期的"模型训练工厂""词元生产工厂""智能体生产工厂"。这套叙事与京东云万卡集群的落地相互印证——摩尔线程的AI算力业务已经从"卖卡"进入"卖集群、卖工厂"的深水区。

技术跃迁的深层逻辑​

回顾国产GPU的发展路径,第一代产品的核心命题是"兼容"——让Linux桌面、办公软件、视频播放跑起来;而"庐山"的命题变成了"范式"——硬件光追对接主流3A管线、AGR参与全球渲染范式变革、AI性能面向大模型时代。从跟随式兼容到范式级参与,这是国产GPU厂商第一次在图形技术方向上与国际一线站在同一条起跑线附近。

AI性能提升64倍的目标也值得放在行业背景下解读:图形与AI本就同源,硬件光追引擎与AI算力单元共享大量基础能力。"庐山"把AI性能提升作为核心指标,说明花港架构在设计之初就为图形+AI双重负载做了统一规划。

小结​

"庐山"GPU承载着摩尔线程的三重跨越:技术上,从软件兼容走向硬件光追与MTAGR 1.0生成式渲染的范式创新;产品上,从单一显卡走向云-边-端全栈布局;商业上,从科创板上市到京东云万卡集群落地,AI算力与游戏GPU双线并进。3A渲染15倍、光追50倍、AI性能64倍的目标能否兑现,要等2026年底产品揭晓(以官方发布为准),但方向已经清晰:国产GPU不再满足于"能用",而是开始追求"领先"。

2nm时代开启:AMD MI455X成首款TSMC N2 AI GPU,三星/台积电2027量产竞速

· 5 min read
Industry Research Team

2nm不再只是制程路线图上的一个名词,它已经成为AI算力竞赛的物理基础。AMD MI455X的问世,宣告最先进制程正式进入AI加速器的主战场。

MI455X:首款N2制程AI GPU登场​

2026年7月23日,AMD在Advancing AI活动中正式发布基于CDNA 5架构的MI455X。而在Hot Chips 2026上,AMD首次公开了这款芯片的chiplet级细节,其中最重磅的信息是:8个加速复杂裸片(XCD)采用台积电N2(2nm)制程制造,这使MI455X成为业界首款采用N2的AI GPU。

N2是台积电首个量产的2nm节点,也是其首次在逻辑制程中采用GAA环绕栅极晶体管的第二代演进。把旗舰AI加速器的主力计算裸片押注在新节点上,AMD对2nm良率与产能的信心可见一斑。

Chiplet架构深度解析​

MI455X的架构设计体现了"异构集成极致化"的思路:

部件制程/规格关键参数
8个XCD计算裸片台积电N2(2nm)3D混合键合(Hybrid Bonding)堆叠
Fabric/Cache/IO裸片台积电N3P承担互连、缓存与外围功能
封装CoWoS-L台积电先进封装
晶体管总数—3200亿
HBM412个堆栈432GB、23.3TB/s带宽
全局L2缓存—192MB

几个值得注意的设计选择:

  • 3D混合键合:8个XCD不再仅靠2.5D互连并排摆放,而是通过3D混合键合垂直堆叠集成,大幅缩短裸片间信号路径、提升互连密度。
  • 制程分工:计算裸片用最先进的N2追求性能与能效,而fabric/cache/IO裸片采用更成熟、成本更低的N3P——这是chiplet时代"好钢用在刀刃上"的典型做法。

内存与算力:对MI355X的代际跃升​

对比上一代MI355X,MI455X在内存和算力两个维度都实现了跨越:

指标MI355X(HBM3E)MI455X(HBM4)提升幅度
显存容量288GB432GB1.5倍
总带宽—23.3TB/s约2.9倍
MXFP4算力—40.26 PFLOPS4倍
MXFP6/MXFP8算力—各20.13 PFLOPS—

低精度数据格式的全面支持是CDNA 5的重点:MXFP4算力达到MI355X的4倍,直接面向当前主流的大模型FP4推理与训练场景。

架构演进:Wave32、超越函数引擎与数据搬运器​

除了制程和规格,MI455X在微架构层面有三处关键改动:

  1. 原生Wave32执行:从传统Wave64转向原生Wave32,降低指令延迟与寄存器压力,让SIMD单元利用率更高,尤其利于注意力机制等不规则计算负载。
  2. 超越函数引擎:新增专用引擎加速attention中的数学运算(如指数、归一化等超越函数),直击Transformer推理的热点。
  3. Tensor Data Mover:专门的数据搬运单元,减少计算单元在数据调度上的空转,提高实际有效算力占比。

这三项改动共同指向一个目标:让纸面PFLOPS尽可能转化为真实吞吐。

2nm量产竞速:台积电、三星与Intel的三角格局​

MI455X只是2nm竞赛的开局。2026年9月的报道显示,三星正联合台积电推进2nm AI芯片制程,目标2027年量产,能效比提升40%。两大代工厂不约而同地把2nm的市场切入点选在AI芯片上——因为只有AI客户能承受先进制程的晶圆成本,也只有AI负载能把每瓦性能的价值放大到极致。

另一边,Intel Foundry的High NA EUV已累计处理超过100万片晶圆(截至2026年9月21日当周的报道),在1.4nm及以下节点上,Intel试图用High NA EUV实现技术反超。代工三强的2nm/1.4nm竞速,本质上是在为2027年之后的AI芯片订单排兵布阵。

能效比:下一个主战场​

为什么整个行业都在押注2nm?答案不是峰值算力,而是能效比。当单个训练集群的功耗达到数百兆瓦时,制程每提升一代带来的每瓦性能改善,会直接折算成电力基建成本和运营费用的下降——这正是前文所述"算力竞赛变成电力竞赛"的技术呼应。三星与台积电宣传的"能效比提升40%",对应的正是客户最痛的那根神经。

小结​

MI455X用8个N2制程XCD、3D混合键合、3200亿晶体管和432GB HBM4,把AI GPU的工程上限推到了新高度;而Wave32原生执行、超越函数引擎和Tensor Data Mover则展示了微架构层面让算力"落地"的努力。随着三星/台积电剑指2027年2nm量产、Intel以High NA EUV蓄力,先进制程与AI算力已经深度捆绑。2nm时代的开启意味着:未来AI芯片的竞争,将在原子尺度上决出胜负。

平头哥公布倚天CPU路线图:倚天720/730明年推出,730首次全自研微架构

· 5 min read
Industry Research Team

在Agentic AI重塑算力需求结构的当下,平头哥首次公开倚天服务器CPU发展蓝图——全自研微架构与ICN总线直连,是这份路线图最值得关注的两个关键词。

云栖大会:倚天蓝图首次公开​

2026年9月22日的云栖大会上,平头哥首次公开倚天系列服务器CPU的发展蓝图:2027年将推出倚天720与倚天730两款服务器CPU。这是平头哥第一次以路线图的形式,系统性地向外界展示倚天CPU的演进节奏——从"发布单点产品"到"公布多代路线",意味着倚天系列的研发与规划已经形成了清晰的代际滚动机制。

型号推出时间核心亮点
倚天710已商用现役主力,后续产品的性能基准
倚天7202027年单核性能、核密度与能效全面提升
倚天7302027年首次基于平头哥全自研CPU微架构设计,单核SPECint2017/GHz性能最高提升至倚天710的1.4倍
倚天750时间未公开基于第二代自研核,支持平头哥自研ICN片间互联总线协议

倚天720与倚天730:差异化分工​

两款2027年的新品各有侧重。倚天720走的是"全面均衡"路线:单核性能、核密度与能效三项指标同步提升,面向通用算力场景的规模化部署——在数据中心机柜功率与空间约束日益收紧的背景下,核密度与能效的提升直接决定了单位机柜可承载的算力上限。

倚天730则是更具突破意义的一代:它首次基于平头哥全自研CPU微架构设计,单核SPECint2017/GHz性能最高提升至倚天710的1.4倍。SPECint2017/GHz衡量的是单位频率下的整数性能(即IPC水平),1.4倍意味着微架构层面的显著优化,而非单纯依靠频率或制程红利。从"基于授权架构"到"全自研微架构",这是服务器CPU自研道路上最关键的一次跨越——它决定了后续每一代产品能否摆脱外部授权的节奏约束。

ICN总线:CPU与AI芯片的直连时代​

路线图中另一个关键角色是ICN片间互联总线协议。根据蓝图,基于第二代自研核的倚天750将支持平头哥自研的ICN总线协议,倚天CPU与真武AI芯片之间可通过ICN总线直接互联,进一步提升CPU与AI芯片的协同效率。

这一设计直指传统架构的痛点:在现有体系中,CPU与AI加速卡之间通常通过PCIe等通用互联通信,带宽与延迟都存在损耗,而这些损耗恰恰发生在数据预处理、梯度同步、通信协同等高频环节。ICN总线让CPU与AI芯片"原生对话",相当于把CPU纳入AI集群的整体互联拓扑,而非让它们停留在AI芯片的"外围"。

Agentic AI时代的CPU需求分化​

平头哥此时公布CPU路线图,并非偶然。其背景是Agentic AI正在驱动CPU需求分化:智能体应用大规模兴起后,CPU不再是AI服务器里"配平"的角色——Agent的调度、编排、数据处理与轻量推理,对CPU的核密度、能效与协同能力都提出了新要求。通用CPU与AI算力的配比、互联方式,都在被重新设计。

同期发布的真武V900构成了这套蓝图的全栈拼图:216GB显存、1200GB/s片间互联、支持50万卡集群。叠加倚天CPU经ICN总线直连的能力,阿里云正在构建"AI芯片+CPU+网络"的全栈算力体系——芯片自研、互联自研、CPU自研,三层能力的耦合度越高,系统的整体效率上限就越高。

小结​

倚天720/730定档2027年、倚天730首次采用全自研微架构、单核SPECint2017/GHz性能最高提升至倚天710的1.4倍,再加上ICN总线与真武AI芯片直连的规划、真武V900(216GB显存、1200GB/s片间互联、50万卡集群)的全栈拼图,平头哥给出了一条清晰且野心不小的CPU自研路线。在Agentic AI驱动的算力变革中,"AI芯片+CPU+网络"的全栈协同能力,或将成为云厂商竞争的下一个分水岭。

昇腾 960 官宣发布:FP4 算力翻倍、全球首个 NPO 超节点,华为确认一年一代

· 6 min read
Industry Research Team

2026 年 9 月 17 日,华为全联接大会(HC2026),华为常务董事、ICT 基础设施业务总裁汪涛正式发布昇腾 960。与 8 月数字中国峰会上的"路线图预告"不同,这次是完整的规格官宣——而且提前三个季度就绪。本文基于华为官网新闻稿及多方报道整理,逐项拆解 960 的规格、超节点与路线图含义。


1. 昇腾 960:双版本,训练先行​

昇腾 960 分为两个版本,节奏错开一个季度:

指标昇腾 960DT(训练版)昇腾 960PR(推理版)
FP8 算力2 PFLOPS(较 950 翻倍)待披露
FP4 算力4 PFLOPS待披露
显存288GB(自研 HBM)待披露
显存带宽9.6 TB/s待披露
配套超节点Atlas 860(风冷)Atlas 960(液冷)
就绪 / 上市2027 Q1 / 2027 Q22027 Q3

三个读数:

  • 提前三个季度就绪:960DT 原计划 2027 年 Q4,现在 2027 Q1 就绪、Q2 上市——与 950DT"提前上线华为云"一脉相承,路线图可信度在持续兑现;
  • 精度口径与英伟达对齐:FP8 / FP4 主口径(辅以自研 HiF8 / HiFP8),FP4 已是 2026 新卡的通用口径;
  • 288GB 自研 HBM + 9.6TB/s:显存容量与带宽同步翻倍,对训练长上下文大模型是实打实的容量红利。

单卡规格详见昇腾 960 规格页;上一代昇腾 950DT 规格页。

2. 昇腾 960 超节点:全球首个 NPO 超节点​

这是本场发布真正的"重器"——昇腾 960 超节点是全球第一个采用 NPO(近封装光学)的超节点:

指标昇腾 960 超节点
单节点规模4096 卡
系统算力8 EFLOPS FP8 / 16 EFLOPS FP4
HBM 总容量1 PB
互联 RTT低至 2μs
可用度99.8%

NPO 意味着什么:传统光模块挂在交换机面板上,信号要先出封装再转电—光;NPO 把光引擎挪到交换芯片封装近旁,大幅缩短 SerDes 距离、降低功耗与时延。华为的具体数字:

  • 5500 个自研 Hi-ONE 光引擎(业界首个量产 NPO,单引擎 7.2T);
  • 替代 4.8 万颗 800G 光模块;
  • 降低功耗 550kW 以上,同时支撑 2μs 级互联时延。

对比 8 月数字中国峰会的口径(Atlas 960 单超节点 15488 卡),官方最新口径为单超节点 4096 卡(1 个超集群可由多超节点组成)——以华为官网最新新闻稿为准。

⚠️ 华为还给出了"MFU 提升 2.75 倍""推理时延降低 70%"等收益数据,均出自华为马尔科夫实验室仿真,尚无独立第三方实测,阅读时注意口径。

3. 一年一代:970(2028)→ 980(2029)​

华为首次把"一年一代"从愿景变成官宣承诺:

年份产品状态
2026昇腾 950 系列950PR 已量产,950DT Q4 放量
2027昇腾 960本次官宣,提前就绪
2028昇腾 970HC2026 确认
2029昇腾 980HC2026 确认

支撑这一节奏的是华为提出的"韬定律":算力规格每代翻倍,访存带宽、访存容量、互联带宽同步大幅提升。

生态侧的同场数据也值得记录:CANN 外部开发者占比首次超过 61%、月活开发者 5200 人;910C 超节点部署已超 1000 套。

4. 竞争坐标:单卡有代差,系统级对打​

把 960DT 放到 2027 年的棋盘上看:

  • 对 NVIDIA Rubin(R200:288GB HBM4 / 50 PFLOPS FP4):单卡 FP4 算力约为 R200 的 8%(4 vs 50 PFLOPS),单卡代差客观存在;但 4096 卡超节点 + NPO 互联是系统级竞争——用"可交付的超大集群"对打单卡性能;
  • 对采购方:960 的价值主张是"在国产量产约束内拿到最大可用集群"。DeepSeek 拟采购 16 万颗 950DT 跑推理的订单已经证明:当供给与生态到位,头部实验室愿意主动选国产;
  • 对国产链条:950→960 的显存翻倍直接拉动国产 HBM 迭代,这是整条链的胜负手。

5. 小结​

  • 960DT:FP8 2P / FP4 4P、288GB HBM、9.6TB/s,2027 Q2 上市,提前三个季度;
  • 960 超节点:全球首个 NPO 超节点,4096 卡 / 8 EFLOPS FP8 / 1PB HBM / RTT 2μs;
  • 路线图:一年一代官宣至 2029,950、960 均提前兑现,规划可信度显著上升;
  • 看什么:2027 Q2 实际交付节奏、国产 HBM 产能、CANN 生态的第三方模型覆盖度。

相关阅读​

参考资料​

  • 华为官网:发布全球首个采用 NPO 的超节点(昇腾 960 超节点)(2026-09-17)
  • 电子工程专辑:国产 AI 芯片新突破!华为昇腾 960 芯片将提前发布
  • 环球网:华为全联接大会 2026 主题演讲报道

本文基于华为官网新闻稿与公开报道整理。MFU、时延等收益数据为华为实验室仿真口径;2028 / 2029 产品仅为路线图官宣,规格以未来发布为准。

AWS Adds Another 2 Million NVIDIA GPUs: Vera CPU Debuts on AWS, 100,000 GPUs Reserved for the U.S. Government AI Factory

· 5 min read
Industry Research Team

This article is based on official announcements from AWS and NVIDIA (September 5, 2026) and public statements by executives of both companies.

On September 5, 2026, AWS and NVIDIA announced an expanded strategic partnership: on top of the "1 million additional GPUs starting in 2026" plan announced at GTC 2026, they will deploy 2 million more NVIDIA GPUs, covering three architecture generations — Blackwell Ultra, Rubin, and Rubin Ultra — with a deployment window of 2027-2028. Demand growth exceeding all previous forecasts was the direct reason both companies cited.

This is no longer a simple "chip purchase" — it is a full-stack partnership spanning GPUs, CPUs, interconnect, memory, open-source models, and software. We break the key information into six points.

1. Composition and Timeline of the 2 Million GPUs​

  • Scale: 2 million GPUs (added on top of the original 1 million GPU plan, tripling the total committed scale)
  • Architectures: Blackwell Ultra, Rubin, Rubin Ultra
  • Timeline: 2027-2028, deployed across AWS global infrastructure (including newly built AI factories)
  • Context: Amazon's 2026 capital expenditure guidance has been raised from $200 billion to $220 billion, and CEO Andy Jassy has explicitly said it is still not enough to meet AI compute demand

For reference, the figures Jensen Huang gave at GTC 2026 put cumulative orders and demand for the Blackwell and Rubin platforms through 2027 on track to reach $1 trillion (at GTC 2025, the estimate for 2026 was roughly $500 billion). AWS's add-on order is one of the heaviest puzzle pieces in that big picture.

2. Vera CPU Comes to AWS for the First Time​

This is the most structurally significant change in the partnership: NVIDIA Vera CPU infrastructure will enter AWS.

The Vera CPU is the general-purpose processor in the Vera Rubin platform designed for agentic AI, positioned to efficiently turn AI resources into "completed agent tasks." As agentic workloads rise, CPU-side pressure on task orchestration, memory management, and data scheduling rises in step — pure GPU expansion is no longer enough, and AWS needs a matching high-performance CPU layer. This also aligns with AWS's strategy of "offering the broadest compute choices, from in-house chips (Graviton/Trainium) to partner chips": Vera does not replace Trainium, but fills in the CPU compute layer alongside the accelerated infrastructure.

At re:Invent 2025, AWS announced that its next-generation Trainium chip would support NVIDIA NVLink Fusion high-speed interconnect. This time, both companies took the partnership one step further:

  • Amazon Annapurna Labs will support NVIDIA's new custom high-bandwidth memory NVHBM (developed in collaboration with memory vendors)
  • Trainium thereby gains a faster, more power-efficient memory option
  • Trainium and GPUs can work together within the same rack-scale architecture, sharing scale-up interconnect

For the chip industry, this is a signal worth watching closely: NVLink Fusion + NVHBM means NVIDIA's interconnect and memory technologies have started "supplying" competing ASICs. The boundary between the in-house ASIC camp (Trainium, TPU, MTIA) and the NVIDIA GPU camp is shifting from "either/or" to "hybrid deployment."

4. 100,000 GPUs: The U.S. Government Sovereign AI Factory​

A dedicated public-sector business is carved out of the partnership: AWS and NVIDIA will build AI factories for the U.S. government, deploying 100,000 GPUs on secure AWS infrastructure to host federal and national security workloads (Impact Level 6 and above), supporting the development of advanced AI models within strict regulatory frameworks.

Sovereign AI turning from a slogan into concrete numbers is a defining feature of this cycle — government customers are becoming first-class buyers of AI compute.

5. Software and Physical AI Deepen in Parallel​

Beyond hardware, the software layer of the partnership is also strengthening:

  • NVIDIA Nemotron open-source models continue to arrive on Amazon Bedrock and SageMaker
  • Amazon EMR data processing and OpenSearch vector indexing are accelerated by cuDF / cuVS
  • Amazon Robotics officially adopts the NVIDIA physical AI platform (Jetson, Omniverse, Isaac) for warehouse automation and next-generation robotics

Physical AI (robotics, embodied intelligence) is becoming a new growth pole in cloud providers' compute narratives — the same trend as JD.com, Tesla, and others writing embodied intelligence into their compute procurement logic.

6. Implications for Compute Buyers​

ObservationImplication
Demand "beat all forecasts"Supply tightness is not a short-term phenomenon; the 2027-2028 compute window must be locked in now
Mixed procurement across three architecturesDuring the Rubin/Rubin Ultra production ramp-up, Blackwell Ultra remains the delivery mainstay; procurement needs cross-generation planning
CPU layer revaluedagentic AI pushes the bottleneck from GPU to CPU orchestration and memory bandwidth; do not focus only on accelerator cards when selecting
Sovereign AI landsGovernment-scale orders enter the market, further tightening the allocatable supply of high-end GPUs

For decision-makers weighing build versus rent, every massive add-on order from cloud giants reprices the future rental curve. If you are evaluating GPU purchase or rental options, we recommend running a quantitative calculation with the TCO Calculator: enter chip price, power draw, utilization, and rental rates to compare 3-year total cost of ownership.

Summary​

2 million GPUs, Vera CPU in the cloud, NVHBM opening up, 100,000 sovereign compute GPUs — this round of expansion between AWS and NVIDIA pushes the "AI factory" race into the full-stack era. Compute scarcity will most likely only tighten before 2027; whether you are buying, renting, or betting on domestic alternatives, locking in supply and cost curves early is the surest move right now.

(The data in this article comes from official AWS/NVIDIA announcements and public statements by executives of both companies; architecture performance figures are as released by the vendors.)

2026 H2 AI Chip Roadmap Major Update: Qualcomm Enters, AMD MI400 Three Models Unveiled, Huawei Three-Generation Roadmap

· 7 min read
AI Hardware Analyst

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.


Key Takeaways​

  • Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
  • AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
  • Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
  • Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
  • NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

ModelLaunchAvailabilityKey Features
AI 1002025-102026 H2Rack-scale AI inference, 768GB LPDDR per card
AI 2502025-102027 H1Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

  1. Low TCO: LPDDR memory is far cheaper than HBM
  2. Energy efficiency: Mobile chip design heritage, excellent power control
  3. Inference-focused: Not chasing training performance, focused on inference scenarios
  4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

  • Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
  • Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
  • Diversifies choice: Breaks NVIDIA's monopoly in the inference market

2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

FeatureSpec
PositioningHPC + sovereign AI
FP32/FP64Supported (key differentiator)
Use casesScientific computing, climate simulation, national AI infrastructure
CompetitorNVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

FeatureSpec
PositioningEnterprise 8-GPU servers
CompatibilityWorks with existing datacenter infrastructure
Use casesEnterprise AI, private cloud, edge inference
AdvantageCheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

FeatureSpec
PositioningFlagship AI training + inference
Optimized precisionFP4/FP8/BF16
Helios rackCore component
CompetitorNVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

  • 18 Zen 6 CPUs (2nm process)
  • 72 MI455X GPUs
  • Direct liquid cooling
  • Shipment expected in 2026 H2

3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

ModelLaunchKey Features
950PR2026-Q1PR (inference-optimized), already in mass production
950DT2026-Q4DT (Decode + training), expected to scale up

Technical highlights:

  • Added FP8/MXFP8/MXFP4 support
  • Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

  • Doubled compute: All specs double versus the 950 series
  • FP8: ~2 PFLOPS expected
  • Process: N+3 (equivalent to 5nm)
  • Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

  • Third-generation flagship: Only timeline announced, specs TBD
  • Significance: Huawei's first complete generation-spanning roadmap
  • Signal: China's domestic AI chips have entered a "roadmap-driven" phase

4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

  • Launch: 2026
  • Architecture: Xe-HPC + Gaudi fusion
  • Process: 18A (Intel's most advanced)
  • Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

  • Possible delay: Some sources suggest a slip to 2027
  • Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
  • Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.


5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

FeatureSpec
HBM288GB HBM4
Compute50 PFLOPS FP4
NVLinkNVLink 6 (1800 GB/s)
ProcessTSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

  • 72 Rubin GPUs
  • 36 Vera CPUs
  • 1.8 EFLOPS FP4
  • Direct liquid cooling

Vera CPU (Debut)​

  • Architecture: Custom CPU replacing Grace
  • Positioning: Deep co-design with Rubin GPU
  • Significance: NVIDIA's transformation from a GPU company into a computing platform company

6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

FeatureTPU 8t (training)TPU 8i (inference)
OptimizationHigh compute, high bandwidthLow latency, low cost
InterconnectOptical interconnectEthernet
Launch20272027

Significance​

  • Industry trend: Specialization of training/inference chips
  • Followers: Qualcomm AI 200 is also inference-only
  • NVIDIA pressure: Does it need an inference-specific chip?

7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

FeatureSpec
Transistors1.4 trillion
Compute125 PFLOPS FP8
Launch2026 H2
ProcessTSMC 5nm

Competitive Advantages​

  • Massive model training: A single WSE-4 can train 10T+ parameter models
  • Low-latency inference: Entire model on one chip, no communication overhead
  • Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

8. Market Landscape Analysis​

Training Market​

RankVendorProductMarket Share (est.)
1NVIDIARubin R20070%
2AMDMI455X15%
3GoogleTPU v8t10%
4HuaweiAscend 9605% (mostly China)

Inference Market (New Battlefield)​

RankVendorProductAdvantage
1NVIDIAH200 / Rubin CPXMature ecosystem
2QualcommAI 200Low TCO
3AMDMI440XGood compatibility
4IntelGaudi 4Low price

Trend 1: Rise of Inference-Specific Chips​

  • Qualcomm AI 200: Mobile giant enters the market
  • NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
  • Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

  • NVIDIA NVL72: 72 GPU + 36 CPU
  • AMD Helios: 18 CPU + 72 GPU
  • Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

  • Huawei three-generation roadmap: 950 → 960 → 970
  • Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
  • Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

  • SK hynix: HBM4 capacity already booked by NVIDIA
  • Samsung: HBM4E samples delivered to AMD
  • Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

10. Procurement Recommendations​

If Procuring in 2026 H2​

  1. Training scenarios:

    • First choice: NVIDIA Rubin R200 (best performance)
    • Alternative: AMD MI455X (better price/performance)
    • Domestic: Huawei Ascend 950DT (China-based customers)
  2. Inference scenarios:

    • First choice: NVIDIA H200 (mature ecosystem)
    • Best value: Qualcomm AI 200 (if available)
    • Cost-sensitive: AMD MI440X
  3. HPC scenarios:

    • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

  • Wait for Rubin Ultra: Performance possibly 2x R200
  • Watch MI500: AMD's next-generation product
  • Evaluate TPU v8: If already on Google Cloud

Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

  • NVIDIA continues to lead, but its advantage is narrowing
  • AMD precisely positions three models; market share will keep rising
  • Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
  • Huawei has a clear three-generation roadmap; domestic substitution accelerates
  • Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.


References​

  • AI Compute Card Future Roadmap - MirrorFrog real-time updates
  • NVIDIA Rubin R200 deep dive (see related articles on this site)
  • AMD MI400 series CES 2026 launch (see related articles on this site)
  • Qualcomm AI 100 launch analysis (coming soon)

Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement